SAK-XC2267M-104F80L AA Infineon Technologies, SAK-XC2267M-104F80L AA Datasheet - Page 40

• Manufacturer Part Number: SAK-XC2267M-104F80L AA
• Description: IC MCU 32BIT FLASH 100-LQFP
• Manufacturer: Infineon Technologies
• Series: XC22xxMr

Specifications of SAK-XC2267M-104F80L AA

• Core Processor: C166SV2
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, LIN, SPI, SSC, UART/USART, USI
• Peripherals: I²S, POR, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 832KB (832K x 8)
• Program Memory Type: FLASH
• Ram Size: 50K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: SP000398034

3.1
The memory space of the XC226xM is configured in the von Neumann architecture. In
this architecture all internal and external resources, including code memory, data
memory, registers and I/O ports, are organized in the same linear address space.
This common memory space consists of 16 Mbytes organized as 256 segments of
64 Kbytes; each segment contains four data pages of 16 Kbytes. The entire memory
space can be accessed bytewise or wordwise. Portions of the on-chip DPRAM and the
register spaces (ESFR/SFR) additionally are directly bit addressable.
The internal data memory areas and the Special Function Register areas (SFR and
ESFR) are mapped into segment 0, the system segment.
The Program Management Unit (PMU) handles all code fetches and, therefore, controls
access to the program memories such as Flash memory and PSRAM.
The Data Management Unit (DMU) handles all data transfers and, therefore, controls
access to the DSRAM and the on-chip peripherals.
Both units (PMU and DMU) are connected to the high-speed system bus so that they can
exchange data. This is required if operands are read from program memory, code or
data is written to the PSRAM, code is fetched from external memory, or data is read from
or written to external resources. These include peripherals on the LXBus such as USIC
or MultiCAN. The system bus allows concurrent two-way communication for maximum
transfer performance.
Table 6
Address Area
IMB register space
Reserved (Access trap) F0’0000
Reserved for EPSRAM E8’8000
Emulated PSRAM
Reserved for PSRAM
Program SRAM
Reserved for Flash
Program Flash 3
Program Flash 2
Program Flash 1
Program Flash 0
External memory area
Available Ext. IO area
Data Sheet
Memory Subsystem and Organization
XC226xM Memory Map
3)
Start Loc.
FF’FF00
E8’0000
E0’8000
E0’0000
CD’0000
CC’0000
C8’0000
C4’0000
C0’0000
40’0000
21’0000
H
H
H
H
H
H
H
H
H
H
H
H
H
End Loc.
FF’FFFF
FF’FEFF
EF’FFFF
E8’7FFF
E7’FFFF
E0’7FFF
DF’FFFF
CC’FFFF
CB’FFFF
C7’FFFF
C3’FFFF
BF’FFFF
3F’FFFF
XC2000 Family Derivatives / Base Line
40
XC2268M/67M, XC2265M/64M/63M
H
H
H
H
H
H
H
H
H
H
H
H
H
Area Size
256 Bytes
<1 Mbyte
480 Kbytes
32 Kbytes
480 Kbytes
32 Kbytes
<1.25 Mbytes –
64 Kbytes
256 Kbytes
256 Kbytes
256 Kbytes
8 Mbytes
< 2 Mbytes
1)
Functional Description
Notes
–
Minus IMB registers
Mirrors EPSRAM
Flash timing
Mirrors PSRAM
Maximum speed
–
–
–
2)
–
Minus USIC/CAN
V2.0, 2009-03