DS80C320-QCG+T&R Maxim Integrated Products, DS80C320-QCG+T&R Datasheet - Page 10

• Manufacturer Part Number: DS80C320-QCG+T&R
• Description: IC MCU HI SPEED 25MHZ 44-PLCC
• Manufacturer: Maxim Integrated Products
• Series: 80Cr

Specifications of DS80C320-QCG+T&R

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SIO, UART/USART
• Peripherals: Power-Fail Reset, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LCC, 44-PLCC
• Processor Series: DS80C320
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Data Ram Size: 64 KB
• Interface Type: UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 4.25 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Table 1. Instruction Set Summary (continued)
*User selectable.
DATA TRANSFER INSTRUCTIONS
MOV A, Rn
MOV A, direct
MOV A, @Ri
MOV A, #data
MOV Rn, A
MOV Rn, direct
MOV Rn, #data
MOV direct, A
MOV direct, Rn
MOV direct1, direct2
MOV direct, @Ri
MOV direct, #data
MOV @Ri, A
MOV @Ri, direct
MOV @Ri, #data
MOV DPTR, #data 16
BIT MANIPULATION INSTRUCTIONS
CLR C
CLR bit
SETB C
SETB bit
CPL C
CPL bit
PROGRAM BRANCHING INSTRUCTIONS
ACALL addr 11
LCALL addr 16
RET
RETI
AJMP addr 11
LJMP addr 16
SJMP rel
JMP @A+DPTR
JZ rel
JNZ rel
DJNZ Rn, rel
DJNZ direct, rel
INSTRUCTION
BYTE
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
2
1
2
1
2
2
3
1
1
2
3
2
1
2
2
2
3
OSCILLATOR
CYCLES
12
12
12
12
16
16
16
12
16
12
12
12
12
12
16
4
8
4
8
8
4
8
8
8
8
8
4
8
8
4
8
4
8
4
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers
10 of 38
MOVC A,
@A+DPTR
MOVC A, @A+PC
MOVX A, @Ri
MOVX A, @DPTR
MOVX @Ri, A
MOVX @DPTR, A
PUSH direct
POP direct
XCH A, Rn
XCH A, direct
XCH A, @Ri
XCHD A, @Ri
ANL C, bit
ANL C,
ORL C, bit
ORL C,
MOV C, bit
MOV bit, C
CJNE A, direct, rel
CJNE A, #data, rel
CJNE Rn, #data, rel
CJNE Ri, #data, rel
NOP
JC rel
JNC rel
JB bit, rel
JNB bit, rel
JBC bit, rel
INSTRUCTION
bit
bit
BYTE
1
1
1
1
1
2
1
1
2
2
2
2
2
2
1
3
1
2
2
1
3
3
3
3
2
2
3
3
OSCILLATOR
CYCLES
8–36*
8–36*
8–36*
8–36*
12
12
16
16
16
16
12
12
16
16
16
8
8
4
8
4
4
8
8
8
8
8
8
4