SAB-C165-LF HA Infineon Technologies, SAB-C165-LF HA Datasheet - Page 69

• Manufacturer Part Number: SAB-C165-LF HA
• Description: IC MCU 16BIT TQFP-100-3
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAB-C165-LF HA

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LFQFP
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: 1xASC, 1xSSC
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 77
• Number Of Timers: 5
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Packages: PG-TQFP-100
• Max Clock Frequency: 20.0 MHz
• Sram (incl. Cache): 2.0 KByte
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: B165LFHAXP; SABC165LFHAX; SP000011595

AC Characteristics
CLKOUT and READY (Standard Supply Voltage)
(Operating Conditions apply)
Parameter
CLKOUT cycle time
CLKOUT high time
CLKOUT low time
CLKOUT rise time
CLKOUT fall time
CLKOUT rising edge to
ALE falling edge
Synchronous READY
setup time to CLKOUT
Synchronous READY
hold time after CLKOUT
Asynchronous READY
low time
Asynchronous READY
setup time
Asynchronous READY
hold time
Async. READY hold time
after RD, WR high
(Demultiplexed Bus)
1)
2)
Data Sheet
These timings are given for test purposes only, in order to assure recognition at a specific clock edge.
Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This
adds even more time for deactivating READY.
The 2
The maximum limit for
t
A
and
1)
1)
t
C
refer to the next following bus cycle,
t
2)
60
must be fulfilled if the next following bus cycle is READY controlled.
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
29
30
31
32
33
34
35
36
37
58
59
60
CC 40
CC 14
CC 10
CC –
CC –
CC 0 +
SR 14
SR 4
SR 54
SR 14
SR 4
SR 0
min.
Max. CPU Clock
t
= 25 MHz
A
65
t
F
refers to the current bus cycle.
max.
40
–
–
4
4
10 +
–
–
–
–
–
0
+ 2
t
+
C
t
F
t
2)
A
t
A
+
1 / 2TCL = 1 to 25 MHz
min.
2TCL
TCL - 6
TCL - 10
–
–
0 +
14
4
2TCL +
14
4
0
Variable CPU Clock
t
A
t
58
–
–
TCL - 20
max.
2TCL
4
4
10 +
–
–
–
–
–
+ 2
+
t
F
t
2)
A
V2.0, 2000-12
t
A
+
t
C
C165
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns