SAK-C164CI-8EM DB Infineon Technologies, SAK-C164CI-8EM DB Datasheet - Page 64

• Manufacturer Part Number: SAK-C164CI-8EM DB
• Description: IC MCU 16BIT 64KB OTP MQFP-80-1
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAK-C164CI-8EM DB

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SPI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: OTP
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-SQFP
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: ASC, CAN, SSC
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Packages: PG-MQFP-80
• Max Clock Frequency: 20.0 MHz
• Sram (incl. Cache): 4.0 KByte
• Can Nodes: 1
• A / D Input Lines (incl. Fadc): 8
• Program Memory: 64.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: K164CI8EMDBNP; K164CI8EMDBXP; SAK-C164CI-8EMDB; SAK-C164CI-8EMDB; SAK-C164CI-8EMDBIN; SAKC164CI8EMDBX; SP000104059

Multiplexed Bus (cont’d)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2
Parameter
ALE fall. edge to RdCS,
WrCS (no RW delay)
Address float after RdCS,
WrCS (with RW delay)
Address float after RdCS,
WrCS (no RW delay)
RdCS to Valid Data In
(with RW delay)
RdCS to Valid Data In
(no RW delay)
RdCS, WrCS Low Time
(with RW delay)
RdCS, WrCS Low Time
(no RW delay)
Data valid to WrCS
Data hold after RdCS
Data float after RdCS
Address hold after
RdCS, WrCS
Data hold after WrCS
1)
Data Sheet
These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
t
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
A
43
44
45
46
47
48
49
50
51
52
54
56
+
t
CC -4 +
CC –
CC –
CC 30 +
CC 50 +
CC 26 +
CC 20 +
CC 20 +
SR –
SR –
SR 0
SR –
C
+
t
F
min.
Max. CPU Clock
(120 ns at 25 MHz CPU clock without waitstates)
= 25 MHz
t
t
t
t
t
t
A
60
C
C
C
F
F
max.
–
0
20
16 +
36 +
–
–
–
–
20 +
–
–
t
t
t
C
C
F
1 / 2TCL = 1 to 25 MHz
min.
-4
+
–
–
–
–
2TCL - 10
+
3TCL - 10
+
2TCL - 14
+
0
–
2TCL - 20
+
2TCL - 20
+
Variable CPU Clock
t
t
t
t
t
t
A
C
C
C
F
F
max.
–
0
TCL
2TCL - 24
+
3TCL - 24
+
–
–
–
–
2TCL - 20
+
–
–
t
t
t
C
C
F
C164CL/SL
V2.0, 2001-05
C164CI/SI
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns