PIC16LC73-04I/SO Microchip Technology, PIC16LC73-04I/SO Datasheet - Page 26

• Manufacturer Part Number: PIC16LC73-04I/SO
• Description: IC PIC MCU 4K 4MHZ OTP 28-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC73-04I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 6 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

PIC16C7X
TABLE 4-2:
DS30390E-page 26
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-
Address Name
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Bank 1
(4)
(4)
(4)
(4)
(5)
(5)
(1,4)
(4)
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
4: These registers can be addressed from either bank.
5: PORTD and PORTE are not physically implemented on the PIC16C73/73A, read as ‘0’.
6: Brown-out Reset is not implemented on the PIC16C73 or the PIC16C74, read as '0'.
7: The IRP and RP1 bits are reserved on the PIC16C73/73A/74/74A, always maintain these bits clear.
INDF
OPTION
PCL
STATUS
FSR
TRISA
TRISB
TRISC
TRISD
TRISE
PCLATH
INTCON
PIE1
PIE2
PCON
PR2
SSPADD
SSPSTAT
TXSTA
SPBRG
ADCON1
Shaded locations are unimplemented, read as ‘0’.
tents are transferred to the upper byte of the program counter.
—
—
—
—
—
—
—
—
—
—
—
PIC16C73/73A/74/74A SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter's (PC) Least Significant Byte
Indirect data memory address pointer
PORTB Data Direction Register
PORTC Data Direction Register
PORTD Data Direction Register
Timer2 Period Register
Synchronous Serial Port (I
Baud Rate Generator Register
PSPIE
RBPU
CSRC
IRP
Bit 7
GIE
IBF
—
—
—
—
—
—
(7)
(3)
INTEDG
RP1
ADIE
PEIE
Bit 6
OBF
TX9
—
—
—
—
—
—
(7)
PORTA Data Direction Register
2
C mode) Address Register
T0CS
TXEN
IBOV
RCIE
Bit 5
T0IE
RP0
D/A
—
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
PSPMODE
SYNC
T0SE
INTE
TXIE
Bit 4
TO
—
—
—
P
SSPIE
RBIE
Bit 3
PSA
PD
—
—
—
—
—
S
PORTE Data Direction Bits
CCP1IE
PCFG2
BRGH
Bit 2
T0IF
PS2
R/W
—
—
Z
TMR2IE
PCFG1
TRMT
INTF
POR
Bit 1
PS1
DC
UA
—
1997 Microchip Technology Inc.
TMR1IE
CCP2IE
PCFG0
BOR
TX9D
RBIF
Bit 0
PS0
BF
C
(6)
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--11 1111 --11 1111
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
0000 -111 0000 -111
---0 0000 ---0 0000
0000 000x 0000 000u
0000 0000 0000 0000
---- ---0 ---- ---0
---- --qq ---- --uu
1111 1111 1111 1111
0000 0000 0000 0000
--00 0000 --00 0000
0000 -010 0000 -010
0000 0000 0000 0000
---- -000
Value on:
POR,
BOR
—
—
—
—
—
—
—
—
—
—
—
other resets
Value on all
---- -000
(2)
—
—
—
—
—
—
—
—
—
—
—