PIC16LC73-04I/SO Microchip Technology, PIC16LC73-04I/SO Datasheet - Page 35

• Manufacturer Part Number: PIC16LC73-04I/SO
• Description: IC PIC MCU 4K 4MHZ OTP 28-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC73-04I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 6 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

4.2.2.5
This register contains the individual flag bits for the
Peripheral interrupts.
FIGURE 4-12: PIR1 REGISTER PIC16C72 (ADDRESS 0Ch)
1997 Microchip Technology Inc.
bit7
bit 7:
bit 6:
bit 5-4: Unimplemented: Read as '0'
bit 3:
bit 2:
bit 1:
bit 0:
U-0
Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the
global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to
enabling an interrupt.
—
PIR1 REGISTER
Applicable Devices
72 73 73A 74 74A 76 77
Unimplemented: Read as '0'
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
SSPIF: Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
R/W-0
ADIF
U-0
—
U-0
—
SSPIF
R/W-0
CCP1IF
R/W-0
TMR2IF
R/W-0
Note:
TMR1IF
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
R/W-0
bit0
W = Writable bit
U = Unimplemented bit,
- n = Value at POR reset
R = Readable bit
read as ‘0’
PIC16C7X
DS30390E-page 35