PIC16LC73-04I/SO Microchip Technology, PIC16LC73-04I/SO Datasheet - Page 68

• Manufacturer Part Number: PIC16LC73-04I/SO
• Description: IC PIC MCU 4K 4MHZ OTP 28-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC73-04I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 6 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

PIC16C7X
8.5
The CCP2 module is not implemented on the
PIC16C72 device.
If the CCP1 or CCP2 module is configured in compare
mode
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer1.
Timer1 must be configured for either timer or synchro-
nized counter mode to take advantage of this feature.
If Timer1 is running in asynchronous counter mode, this
reset operation may not work.
In the event that a write to Timer1 coincides with a spe-
cial event trigger from CCP1 or CCP2, the write will
take precedence.
In this mode of operation, the CCPRxH:CCPRxL regis-
ters pair effectively becomes the period register for
Timer1.
TABLE 8-2:
DS30390E-page 68
Address
0Bh,8Bh,
10Bh,18Bh
0Ch
8Ch
0Eh
0Fh
10h
Legend:
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear.
Note:
2: The PIC16C72 does not have a Parallel Slave Port or a USART, these bits are unimplemented, read as '0'.
to
Resetting Timer1 using a CCP Trigger
Output
Applicable Devices
72 73 73A 74 74A 76 77
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
The special event triggers from the CCP1
and CCP2 modules will not set interrupt
flag bit TMR1IF (PIR1<0>).
Name
INTCON
PIR1
PIE1
TMR1L
TMR1H
T1CON
generate
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
PSPIF
PSPIE
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
Bit 7
a
GIE
—
(1,2)
(1,2)
“special
PEIE
ADIF
ADIE
Bit 6
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
event
RCIE
RCIF
Bit 5
T0IE
(2)
(2)
trigger"
TXIF
TXIE
INTE
Bit 4
(2)
(2)
SSPIE
SSPIF
RBIE
Bit 3
8.6
TMR1H and TMR1L registers are not reset to 00h on a
POR or any other reset except by the CCP1 and CCP2
special event triggers.
T1CON register is reset to 00h on a Power-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other resets, the register is
unaffected.
8.7
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
CCP1IF
CCP1IE
Resetting of Timer1 Register Pair
(TMR1H, TMR1L)
Timer1 Prescaler
Applicable Devices
72 73 73A 74 74A 76 77
Applicable Devices
72 73 73A 74 74A 76 77
Bit 2
T0IF
TMR2IF
TMR2IE
Bit 1
INTF
1997 Microchip Technology Inc.
TMR1IE
TMR1IF
RBIF
Bit 0
0000 000x 0000 000u
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Value on:
POR,
BOR
Value on
all other
resets