AT90S1200-12YC Atmel, AT90S1200-12YC Datasheet
AT90S1200-12YC
Specifications of AT90S1200-12YC
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AT90S1200-12YC Summary of contents
Page 1
... Programmable I/O Lines – 20-pin PDIP, SOIC and SSOP • Operating Voltages – 2.7 - 6.0V (AT90S1200-4) – 4.0 - 6.0V (AT90S1200-12) • Speed Grades – MHz, (AT90S1200-4) – MHz, (AT90S1200-12) Pin Configuration 8-bit Microcontroller with 1K Byte of In-System Programmable Flash AT90S1200 Rev. 0838H–AVR–03/02 ...
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... Description Block Diagram AT90S1200 2 The AT90S1200 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the AT90S1200 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. ...
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... The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not active. Port D also serves the functions of various special features of the AT90S1200 as listed on page 34. Reset input. A low level on this pin for more than 50 ns will generate a reset, even if the clock is not running ...
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... MCU clock source. If enabled, the AT90S1200 can operate with no external compo- nents. A control bit (RCEN) in the Flash Memory selects the On-chip RC Oscillator as the clock source when programmed (“0”). The AT90S1200 is normally shipped with this bit unprogrammed (“1”). Parts with this bit programmed can be ordered as AT90S1200A ...
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... The ALU supports arithmetic and logic functions between registers or between a con- stant and a register. Single register operations are also executed in the ALU. Figure 4 shows the AT90S1200 AVR RISC microcontroller architecture. The AVR uses a Har- vard architecture concept – with separate memories and buses for program and data memories ...
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... Since all instructions are single 16-bit words, the Flash is organized as 512 x 16. The Flash memory has an endurance of at least 1000 write/erase cycles. The AT90S1200 Program Counter is 9 bits wide, thus addressing the 512 words Flash program memory. See page 37 for a detailed description on Flash data downloading. ...
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... The AT90S1200 AVR RISC Microcontroller supports powerful and efficient addressing modes. This section describes the different addressing modes supported in the AT90S1200. In the figures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact location of the addressing bits. ...
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... Program execution continues at address The relative address k is -2048 to 2047. The AT90S1200 uses a 3 level deep hardware stack for subroutines and interrupts. The hardware stack is 9 bits wide and stores the Program Counter (PC) return address while subroutines and interrupts are executed. ...
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... Instruction Execution Timing 0838H–AVR–03/02 The AT90S1200 contains 64 bytes of data EEPROM memory organized as a sepa- rate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described on page 25 specifying the EEPROM address register, the EEPROM data register, and the EEPROM control register ...
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... Note: Reserved and unused locations are not shown in the table. All AT90S1200 I/Os and peripherals are placed in the I/O space. The different I/O loca- tions are accessed by the IN and OUT instructions transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions ...
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... The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set description for detailed information. Note that the status register is not automatically stored when entering an interrupt rou- tine and restored when returning from an interrupt routine. This must be handled by software. AT90S1200 ...
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... Reset Sources AT90S1200 12 The AT90S1200 provides three different interrupt sources. These interrupts and the separate reset vector, each have a separate program vector in the program memory space. All the interrupts are assigned individual enable bits that must be set (one) together with the I-bit in the Status Register in order to enable the interrupt. ...
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... POT VCC V RST RESET t TOUT TIME-OUT INTERNAL RESET If the built-in start-up delay is sufficient, RESET can be connected external pull-up resistor. By holding the RESET pin low for a period after V AT90S1200 POR Time-out 14-stage Ripple Counter = 5.0V) Min Typ 0.8 1.2 0.2 0.4 – ...
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... External Reset Watchdog Reset AT90S1200 14 been applied, the Power-on Reset period can be extended. Refer to Figure 15 for a tim- ing example on this. Figure 15. MCU Start-up, RESET Controlled Externally V POT VCC RESET TIME-OUT INTERNAL RESET An External Reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running ...
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... Note that the Status Register is not automatically stored when entering an interrupt rou- tine and restored when returning from an interrupt routine. This must be handled by software. Bit $3B - INT0 - Read/Write R R/W R Initial Value • Bit 7 – Res: Reserved Bit This bit is a reserved bit in the AT90S1200 and always reads as zero. AT90S1200 ...
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... Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector $002) is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register (TIFR). • Bit 0 – Res: Reserved Bit This bit is a reserved bit in the AT90S1200 and always reads as zero. Bit 7 6 ...
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... Note that the Subroutine and Interrupt Stack is a 3-level true hardware stack, and if more than three nested subroutines and interrupts are executed, only the most recent three return addresses are stored. AT90S1200 17 ...
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... For details, refer to the paragraph “Sleep Modes” on the following page. • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the AT90S1200 and always read as zero. • Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask in the GIMSK register is set ...
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... Reset (if enabled), an external level interrupt on INT0 can wake up the MCU. Note that when a level triggered interrupt is used for wake-up from Power-down, the low level must be held for a time longer than the reset delay time-out period t wise, the device will not wake up. AT90S1200 . Other- TOUT 19 ...
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... Timer/Counter0 Timer/Counter0 Prescaler AT90S1200 T90 Timer/Counter0 gets the prescaled clock from the 10-bit prescaling timer. The Timer/Counter0 can either be used as a Timer with an internal clock time base Counter with an external pin connection, which triggers the counting. Figure 18 shows the general Timer/Counter0 prescaler. ...
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... Timer/Counter0 useful for lower speed functions or exact timing functions with infre- quent actions. Bit $ Read/Write Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90S1200 and always read as zero. AT90S1200 CS02 CS01 CS00 R R R/W R/W R ...
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... Timer/Counter0 – TCNT0 AT90S1200 22 • Bits – CS02, CS01, CS00: Clock Select0, Bits 2, 1 and 0 The Clock Select0 bits 2, 1 and 0 define the prescaling source of Timer/Counter0. Table 5. Clock 0 Prescale Select CS02 CS01 CS00 The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the CK Oscillator clock ...
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... Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the AT90S1200 and will always read as zero. • Bit 3 – WDE: Watchdog Enable When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. ...
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... AT90S1200 24 Table 6. Watchdog Timer Prescale Select Number of WDT WDP2 WDP1 WDP0 Oscillator Cycles 16K cycles 32K cycles 64K cycles 128K cycles 256K cycles 512K cycles 1,024K cycles 2,048K cycles Note: The frequency of the Watchdog Oscillator is voltage dependent as shown in “Typical Characteristics” on page 51. ...
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... Read/Write Initial Value • Bits 7..2 – Res: Reserved Bits These bits are reserved bits in the AT90S1200 and will always be read as zero. AT90S1200 is likely to rise or fall slowly on Power EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 R/W R/W R/W R/W ...
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... Prevent EEPROM Corruption AT90S1200 26 • Bit 1 – EEWE: EEPROM Write Enable The EEPROM Write Enable Signal (EEWE) is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. When the write access time (typically 2 ...
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... Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise, an interrupt can occur when the bit is changed. • Bit 6 – Res: Reserved Bit This bit is a reserved bit in the AT90S1200 and will always read as zero. • Bit 5 – ACO: Analog Comparator Output ACO is directly connected to the comparator output. ...
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... Comparator Interrupt is activated. When cleared (zero), the interrupt is disabled. • Bit 2 – Res: Reserved Bit This bit is a reserved bit in the AT90S1200 and will always read as zero. • Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events trigger the Analog Comparator Interrupt. ...
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... N/A The Port B Input Pins address (PINB) is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read. AT90S1200 ...
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... Port B as General Digital I/O Alternate Functions of Port B AT90S1200 30 All eight pins in Port B have equal functionality when used as digital I/O pins. PBn, General I/O pin: The DDBn bit in the DDRB Register selects the direction of this pin, if DDBn is set (one), PBn is configured as an output pin. If DDBn is cleared (zero), PBn is configured as an input pin ...
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... Port B Schematics 0838H–AVR–03/02 Note that all port pins are synchronized. The synchronization latches are, however, not shown in the figures. Figure 22. Port B Schematic Diagram (Pins PB0 and PB1) AT90S1200 31 ...
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... AT90S1200 32 Figure 23. Port B Schematic Diagram (Pins PB2, PB3, and PB4) 2, Figure 24. Port B Schematic Diagram (Pin PB5) 0838H–AVR–03/02 ...
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... Figure 25. Port B Schematic Diagram (Pin PB6) Figure 26. Port B Schematic Diagram (Pin PB7) AT90S1200 33 ...
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... DDRD Port D Input Pins Address – PIND Port D as General Digital I/O AT90S1200 34 Three I/O memory address locations are allocated for Port D, one each for the Data Register – PORTD ($12), Data Direction Register – DDRD ($11), and the Port D Input Pins – PIND ($10). The Port D Input Pins address is read-only, while the Data Register and the Data Direction Register are read/write ...
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... INT0, External Interrupt source 0. See the interrupt description for further details. Note that all port pins are synchronized. The synchronization latches are, however, not shown in the figures. Figure 27. Port D Schematic Diagram (Pins PD0, PD1, PD3, PD5, and PD6) AT90S1200 Comment No Tri-state (High-Z) Yes PDn will source current if ext ...
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... AT90S1200 36 Figure 28. Port D Schematic Diagram (Pin PD2) Figure 29. Port D Schematic Diagram (Pin PD4) MOS PULL- UP PD4 WP: WRITE PORTD WD: WRITE DDRD RL: READ PORTD LATCH RP: READ PORTD PIN RD: READ DDRD RD RESET DDD4 C WD RESET PORTD4 TIMER0 CLOCK SENSE CONTROL SOURCE MUX CS00 CS02 CS01 0838H– ...
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... Programming the Flash and EEPROM 0838H–AVR–03/02 The AT90S1200 MCU provides two Lock bits that can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 12. The Lock bits can only be erased with the Chip Erase command. ...
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... EEPROM data memory, Lock bits and Fuse bits in the AT90S1200. Figure 30. Parallel Programming In this section, some pins of the AT90S1200 are referenced by signal names describing their function during parallel programming rather than their pin names, see Figure 30 and Table 14. Pins not described in Table 14 are referenced by pin names. ...
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... Table 17. Chip Erase does not generate any activity on the RDY/BSY pin. A: Load Command “Write Flash” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS to “0”. 3. Set DATA to “0001 0000”. This is the command for Write Flash. AT90S1200 Command Executed Chip Erase Write Fuse Bits Write Lock Bits ...
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... AT90S1200 40 4. Give XTAL1 a positive pulse. This loads the command. B: Load Address High Byte 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS to “1”. This selects high byte. 3. Set DATA = Address high byte ($00 - $01). 4. Give XTAL1 a positive pulse. This loads the address high byte. ...
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... C: Load Address Low Byte ($00 - $FF). 4. Set OE to “0”, and BS to “0”. The Flash word low byte can now be read at DATA. 5. Set BS to “1”. The Flash word high byte can now be read from DATA. 6. Set OE to “1”. AT90S1200 ADDR.LOW DATA LOW 41 ...
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... Programming the Fuse Bits Programming the Lock Bits Reading the Fuse and Lock Bits AT90S1200 42 The programming algorithm for the EEPROM data memory is as follows (refer to “Pro- gramming the Flash” for details on command, address and data loading Load Command “0001 0001”. ...
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... OHDZ t WR Pulse Width Low for Chip Erase WLWH_CE t WR Pulse Width Low for Programming the Fuse WLWH_PFB Bits Notes: 1. Use t for chip erase and t WLWH_CE held longer than t WLWH AT90S1200 t XLWL t t XLDX BVWL t WLWH t WHRL t XLOL t OLDV = 25 ° C ± 10%, V ...
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... Low: > 1 XTAL1 clock cycle High: > 4 XTAL1 clock cycles When writing serial data to the AT90S1200, data is clocked on the rising edge of SCK. When reading data from the AT90S1200, data is clocked on the falling edge of SCK. See Figure 35 and Table 20 for timing details. ...
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... This will not work for the value $FF, so when programming this value, the user will have to wait for at least t WD_PROG erased device contains $FF in all locations, programming of addresses that are meant to contain $FF, can be skipped. AT90S1200 WD_ERASE value. WD_PROG before programming the next byte. See Table 22 ...
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... Figure 35. Serial Programming Waveforms Table 19. Serial Programming Instruction Set for AT90S1200 Instruction Byte 1 Programming 1010 1100 0101 0011 Enable Chip Erase 1010 1100 100x xxxx Read Program 0010 H000 0000 000a Memory Write Program 0100 H000 0000 000a Memory Read EEPROM ...
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... SHOX t SCK Low to MISO Valid SLIV Table 21. Minimum Wait Delay after the Chip Erase Instruction Symbol 3. WD_ERASE Table 22. Minimum Wait Delay after Writing a Flash or EEPROM Location Symbol 3. WD_PROG AT90S1200 t t SLSH SHOX t SHSL t SLIV = -40 ° ° Min Typ = 2.7 - 4.0V) 0 250 ...
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... Current I/O pin I Input Leakage IH Current I/O pin RRST Reset Pull-up Resistor R I/O Pin Pull-up Resistor I/O I Power Supply Current CC (5) I Power-down mode CC AT90S1200 48 *NOTICE: +0.5V CC Condition Min (Except XTAL1) -0.5 (XTAL1) -0.5 (Except XTAL1, RESET) 0.6 V (XTAL1) 0.7 V (RESET) 0.85 V ...
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... 2. 4.0V CC may exceed the related specification. Pins are not guaranteed to sink current greater OL may exceed the related specification. Pins are not guaranteed to source current OH AT90S1200 Typ Max Units 40.0 50.0 750.0 500 3V) under steady state 5V, 1 3V) under steady state CC CC ...
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... External Clock Drive Waveforms External Clock Drive AT90S1200 50 Figure 37. External Clock Drive VIH1 VIL1 Table 23. External Clock Drive Symbol Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time CLCX t Rise Time CLCH t Fall Time CHCL V = 2. ...
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... The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the dif- ferential current drawn by the Watchdog Timer. Figure 38. Active Supply Current vs. Frequency ACTIVE SUPPLY CURRENT vs. FREQUENCY AT90S1200 = operating voltage and f = average 25˚ 2. Frequency (MHz ...
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... AT90S1200 52 Figure 39. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs 2.5 3 3.5 Figure 40. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs. V DEVICE CLOCKED BY INTERNAL RC OSCILLATOR 2 FREQUENCY = 4 MHz 4.5 5 5 Device Clocked by Internal Oscillator ˚ 4.5 5 5 ˚ ˚ ˚ ˚ ...
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... Figure 41. Idle Supply Current vs. Frequency IDLE SUPPLY CURRENT vs. FREQUENCY 4.5 4 3.5 3 2.5 2 1 Figure 42. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs. V 2.5 2 1 2.5 3 3.5 AT90S1200 T = 25˚ 2. Frequency (MHz FREQUENCY = 4 MHz 4 4.5 5 5 5.5V ...
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... AT90S1200 54 Figure 43. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs. V DEVICE CLOCKED BY INTERNAL RC OSCILLATOR 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0. 2.5 3 3.5 Figure 44. Power-down Supply Current vs. V POWER DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER DISABLED 1.8 1.6 1.4 1.2 1 0.8 ...
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... POWER DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED 140 120 100 2.5 3 3.5 Figure 46. Internal RC Oscillator Frequency vs. V INTERNAL RC OSCILLATOR FREQUENCY vs. V 1600 1400 1200 1000 800 600 400 200 0 2 2.5 3 3.5 AT90S1200 , Watchdog Timer Enabled ˚ 4.5 5 5 ˚ ˚ 4 ...
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... AT90S1200 56 Figure 47. Analog Comparator Current vs. V ANALOG COMPARATOR CURRENT vs. V 1.2 1 0.8 0.6 0.4 0 2.5 3 3.5 Note: Analog comparator offset voltage is measured as absolute offset. Figure 48. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE 0.5 1 1.5 ...
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... Figure 49. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE 0.5 1 Common Mode Voltage (V) Figure 50. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT -10 0 0.5 1 1.5 2 2.5 AT90S1200 ˚ 1 ˚ 3.5 4 4.5 5 5.5 6 6 ˚ ...
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... AT90S1200 58 Note: Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 51. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE 120 ˚ A 100 ˚ 0.5 1 1.5 Figure 52. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE ...
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... Figure 53. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 0.5 1 Figure 54. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE ˚ ˚ 0.5 1 1.5 AT90S1200 ˚ ˚ A 1.5 2 2 2.5 3 3.5 4 4 ...
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... AT90S1200 60 Figure 55. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 0.5 Figure 56. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE ˚ ˚ 0 2. ˚ ˚ 1 2.7V cc 1.5 2 2.5 V (V) OH 0838H–AVR–03/02 ...
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... Figure 57. I/O Pin Input Threshold Voltage vs. V I/O PIN INPUT THRESHOLD VOLTAGE vs. V 2.5 2 1.5 1 0.5 0 2.7 Figure 58. I/O Pin Input Hysteresis vs. V I/O PIN INPUT HYSTERESIS vs. V 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 2.7 AT90S1200 ˚ A 4.0 5 ˚ A 4.0 5 ...
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... AT90S1200 Register Summary Address Name Bit 7 $3F SREG $3E Reserved $3D Reserved $3C Reserved $3B GIMSK $3A Reserved $39 TIMSK $38 TIFR $37 Reserved $36 Reserved $35 MCUCR $34 Reserved $33 TCCR0 $32 TCNT0 $31 Reserved $30 Reserved $2F Reserved $2E Reserved $2D Reserved $2C Reserved $2B Reserved $2A Reserved $29 Reserved $28 Reserved $27 Reserved $26 Reserved $25 Reserved $24 Reserved $23 Reserved $22 Reserved $21 WDTCR $20 Reserved $1F Reserved $1E EEAR ...
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... ← then ← then ← then ← then ← then ← then ← Rd (Z) ← (Z) Rr ← ← ← ← AT90S1200 Flags # Clocks Z,C,N,V,H 1 Z,C,N,V,H 1 Z,C,N,V,H 1 Z,C,N,V,H 1 Z,C,N,V,H 1 Z,C,N,V,H 1 Z,N,V 1 Z,N,V 1 Z,N,V 1 Z,N,V 1 Z,N,V 1 Z,C,N,V 1 Z,C,N,V,H 1 Z,N,V 1 Z,N,V 1 Z,N,V 1 Z,N,V 1 Z,N,V ...
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... Clear Two’s Complement Overflow SET Set T in SREG CLT Clear T in SREG SEH Set Half-carry Flag in SREG CLH Clear Half-carry Flag in SREG NOP No Operation SLEEP Sleep WDR Watchdog Reset AT90S1200 64 Operation ← I/O(P,b) 1 ← I/O(P,b) 0 ← ← Rd(n+1) Rd(n), Rd(0) 0 ← ...
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... AT90S1200-4PC 20P3 AT90S1200-4SC 20S AT90S1200-4YC 20Y AT90S1200-4PI 20P3 AT90S1200-4SI 20S AT90S1200-4YI 20Y AT90S1200-12PC 20P3 AT90S1200-12SC 20S AT90S1200-12YC 20Y AT90S1200-12PI 20P3 AT90S1200-12SI 20S AT90S1200-12YI 20Y Package Type AT90S1200 Operation Range Commercial (0°C to 70°C) Industrial (-40°C to 85°C) Commercial (0°C to 70°C) Industrial (-40° ...
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... Packaging Information 20P3 A SEATING PLANE L e Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R AT90S1200 66 D PIN TITLE 20P3, 20-lead (0.300" ...
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... PIN 1 ID PIN 1 1.27 (0.050) BSC 13.00 (0.5118) 12.60 (0.4961) 0.30(0.0118) 0.10 (0.0040) 0º ~ 8º 1.27 (0.050) 0.40 (0.016) *Controlling dimension: Inches AT90S1200 10.65 (0.419) 7.60 (0.2992) 10.00 (0.394) 7.40 (0.2914) 2.65 (0.1043) 2.35 (0.0926) 0.32 (0.0125) 0.23 (0.0091) 67 ...
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... Plastic Shrink Small Outline (SSOP), 5.3mm body Width. Dimensions in Millimeters and (inches)* PIN 1 ID REV. A 04/11/2001 AT90S1200 68 0.38 (0.015) 0.25 (0.010) PIN 1 0.65 (0.0256) BSC 7.33 (0.289) 7.07 (0.278) 0.21 (0.008) 0.05 (0.002) 0º ~ 8º 0.95 (0.037) 0.63 (0.025) *Controlling dimension: millimeters 5 ...
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... EEPROM Read/Write Access............................................................. 25 Prevent EEPROM Corruption ............................................................................. 26 Analog Comparator ............................................................................ 27 I/O Ports............................................................................................... 29 Port B.................................................................................................................. 29 Port D.................................................................................................................. 34 Memory Programming........................................................................ 37 Program and Data Memory Lock Bits................................................................. 37 Fuse Bits............................................................................................................. 37 Signature Bytes .................................................................................................. 37 Programming the Flash and EEPROM............................................................... 37 Parallel Programming ......................................................................................... 38 Parallel Programming Characteristics ................................................................ 43 Serial Downloading............................................................................................. 44 Serial Programming Characteristics ................................................................... 47 AT90S1200 i ...
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... AT90S1200 ii Electrical Characteristics................................................................... 48 Absolute Maximum Ratings*............................................................................... 48 DC Characteristics.............................................................................................. 48 External Clock Drive Waveforms ........................................................................ 50 External Clock Drive ........................................................................................... 50 Typical Characteristics ...................................................................... 51 AT90S1200 Register Summary.......................................................... 62 Instruction Set Summary ................................................................... 63 (1) Ordering Information ....................................................................... 65 Packaging Information ....................................................................... 66 20P3 ................................................................................................................... 66 20S ..................................................................................................................... 67 20Y ..................................................................................................................... 68 Table of Contents .................................................................................. i 0838H–AVR–03/02 ...
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... No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ...