AT90S1200-12YC Atmel, AT90S1200-12YC Datasheet - Page 16

• Manufacturer Part Number: AT90S1200-12YC
• Description: IC MCU 1K FLSH 12MHZ 20SSOP
• Manufacturer: Atmel
• Series: AVR® 90Sr

Specifications of AT90S1200-12YC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: SPI
• Peripherals: POR, WDT
• Number Of I /o: 15
• Program Memory Size: 1KB (512 x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Ram Size: -
• Data Converters: -

Timer/Counter Interrupt Mask
Register
Timer/Counter Interrupt FLAG
Register
16
–
–
AT90S1200
TIMSK
TIFR
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control0 bit 1/0 (ISC01 and
ISC00) in the MCU general Control Register (MCUCR) defines whether the external
interrupt is activated on rising or falling edge of the INT0 pin or low level sensed. INT0
can be activated even if the pin is configured as an output. See also page 17.
• Bits 5..0 – Res: Reserved Bits
These bits are reserved bits in the AT90S1200 and always read as zero.
• Bits 7..2 – Res: Reserved Bits
These bits are reserved bits in the AT90S1200 and always read as zero.
• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector
$002) is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set
in the Timer/Counter Interrupt Flag Register (TIFR).
• Bit 0 – Res: Reserved Bit
This bit is a reserved bit in the AT90S1200 and always reads as zero.
• Bits 7..2 – Res: Reserved Bits
These bits are reserved bits in the AT90S1200 and always read as zero.
• Bit 1 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE0
(Timer/Counter0 O ver flow Interrupt Enable), and TOV0 ar e set ( one), the
Timer/Counter0 Overflow interrupt is executed.
• Bit 0 – Res: Reserved Bit
This bit is a reserved bit in the AT90S1200 and always reads as zero.
Bit
$39
Read/Write
Initial Value
Bit
$38
Read/Write
Initial Value
R
7
0
-
R
7
0
-
R
6
0
R
-
6
0
-
5
R
0
-
R
5
0
-
R
4
0
-
R
4
0
-
R
3
0
-
R
3
0
-
R
2
0
-
R
2
0
-
TOIE0
R/W
1
0
TOV0
R/W
1
0
R
0
0
0838H–AVR–03/02
-
R
0
0
-
TIMSK
TIFR