AT90S4433-8PC Atmel, AT90S4433-8PC Datasheet - Page 27

• Manufacturer Part Number: AT90S4433-8PC
• Description: IC MCU 4K FLSH 8MHZ A/D 28DIP
• Manufacturer: Atmel
• Series: AVR® 90Sr

Specifications of AT90S4433-8PC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

General Interrupt Mask
Register – GIMSK
General Interrupt Flag
Register – GIFR
1042H–AVR–04/03
Note that the Status Register is not automatically stored when entering an interrupt rou-
tine or restored when returning from an interrupt routine. This must be handled by
software.
• Bit 7 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and
ISC10) in the MCU General Control Register (MCUCR) defines whether the External
Interrupt is activated on rising or falling edge of the INT1 pin or is level sensed. Please
note that INTF1 Flag is not set when the level-sensitive interrupt condition is met. How-
ever, INT1 interrupt is generated, provided that INT1 mask bit is set in GIMSK Register.
Activity on the pin will cause an interrupt request even if INT1 is configured as an output.
The corresponding interrupt of External Interrupt Request 1 is executed from program
memory address $002. See also “External Interrupts”.
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and
ISC00) in the MCU General Control Register (MCUCR) defines whether the External
Interrupt is activated on rising or falling edge of the INT0 pin or is level sensed. Please
note that INTF0 Flag is not set when the level-sensitive interrupt condition is met. How-
ever, INT0 interrupt is generated, provided that INT0 mask bit is set in GIMSK Register.
Activity on the pin will cause an interrupt request even if INT0 is configured as an output.
The corresponding interrupt of External Interrupt Request 0 is executed from program
memory address $001. See also “External Interrupts”.
• Bits 5..0 – Res: Reserved Bits
These bits are reserved bits in the AT90S4433 and always read as zero.
• Bit 7 – INTF1: External Interrupt Flag1
When an edge on the INT1 pin triggers an interrupt request, the corresponding interrupt
flag, INTF1 becomes set (one). If the I-bit in SREG and the corresponding interrupt
enable bit, INT1 in GIMSK, is set (one), the MCU will jump to the Interrupt Vector. The
flag is always cleared when the interrupt routine is executed. Alternatively, the flag is
cleared by writing a logical “1” to it. This flag is always cleared when INT1 is configured
as level interrupt.
Bit
$3B ($5B)
Read/Write
Initial Value
Bit
$3A ($5A)
Read/Write
Initial Value
INTF1
INT1
R/W
R/W
7
0
7
0
INTF0
INT0
R/W
R/W
6
0
6
0
R
R
5
–
0
5
–
0
R
R
4
–
0
4
–
0
R
R
3
–
0
3
–
0
R
R
2
–
0
2
–
0
AT90S/LS4433
R
R
1
–
0
1
–
0
R
R
0
–
0
0
–
0
GIMSK
GIFR
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