AT90S4433-8PC Atmel, AT90S4433-8PC Datasheet - Page 43

• Manufacturer Part Number: AT90S4433-8PC
• Description: IC MCU 4K FLSH 8MHZ A/D 28DIP
• Manufacturer: Atmel
• Series: AVR® 90Sr

Specifications of AT90S4433-8PC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Watchdog Timer
Watchdog Timer Control
Register – WDTCR
1042H–AVR–04/03
The Watchdog Timer is clocked from a separate On-chip Oscillator. By controlling the
Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in
Table 6. See characterization data for typical values at other V
(Watchdog Reset) instruction resets the Watchdog Timer. Eight different clock cycle
periods can be selected to determine the reset period. If the reset period expires without
another Watchdog Reset, the AT90S4433 resets and executes from the Reset vector.
For timing details on the Watchdog Reset, refer to page 25.
To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be
followed when the Watchdog is disabled. Refer to the description of the Watchdog Timer
Control Register for details.
Figure 35. Watchdog Timer
• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the AT90S4433 and will always read as zero.
• Bit 4 – WDTOE: Watchdog Turn-off Enable
This bit must be set (one) when the WDE bit is cleared. Otherwise, the Watchdog will
not be disabled. Once set, hardware will clear this bit to zero after four clock cycles.
Refer to the description of the WDE bit for a Watchdog disable procedure.
• Bit 3 – WDE: Watchdog Enable
When the WDE is set (one), the Watchdog Timer is enabled; if the WDE is cleared
(zero), the Watchdog Timer function is disabled. WDE can only be cleared if the
WDTOE bit is set (one). To disable an enabled Watchdog Timer, the following proce-
dure must be followed:
1. In the same operation, write a logical “1” to WDTOE and WDE. A logical “1” must
2. Within the next four clock cycles, write a logical “0” to WDE. This disables the
Bit
$21 ($41)
Read/Write
Initial Value
be written to WDE even though it is set to one before the disable operation
starts.
Watchdog.
R
7
–
0
R
6
–
0
R
5
–
0
WDTOE
R/W
4
0
WDE
R/W
3
0
WDP2
R/W
2
0
AT90S/LS4433
WDP1
R/W
1
0
CC
levels. The WDR
WDP0
R/W
0
0
WDTCR
43