PIC17LC756AT-08/L Microchip Technology, PIC17LC756AT-08/L Datasheet - Page 102

• Manufacturer Part Number: PIC17LC756AT-08/L
• Description: IC MCU OTP 16KX16 A/D 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17LC756AT-08/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• Processor Series: PIC17LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 902 B
• Interface Type: I2C, MSSP, RS- 232, SCI, SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 8
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 12 bit
• Data Rom Size: 902 B
• Height: 4.06 mm
• Length: 24.33 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 3 V
• Width: 24.33 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC17C7XX
REGISTER 13-2: TCON2 REGISTER (ADDRESS: 17h, BANK 3)
DS30289B-page 102
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Legend:
R = Readable bit
- n = Value at POR Reset
bit 7
CA2OVF: Capture2 Overflow Status bit
This bit indicates that the capture value had not been read from the capture register pair
(CA2H:CA2L) before the next capture event occurred. The capture register retains the oldest
unread capture value (last capture before overflow). Subsequent capture events will not update
the capture register with the TMR3 value until the capture register has been read (both bytes).
1 = Overflow occurred on Capture2 register
0 = No overflow occurred on Capture2 register
CA1OVF: Capture1 Overflow Status bit
This bit indicates that the capture value had not been read from the capture register pair (PR3H/
CA1H:PR3L/CA1L), before the next capture event occurred. The capture register retains the old-
est unread capture value (last capture before overflow). Subsequent capture events will not
update the capture register with the TMR3 value until the capture register has been read (both
bytes).
1 = Overflow occurred on Capture1 register
0 = No overflow occurred on Capture1 register
PWM2ON: PWM2 On bit
1 = PWM2 is enabled
0 = PWM2 is disabled
PWM1ON: PWM1 On bit
1 = PWM1 is enabled
0 = PWM1 is disabled
CA1/PR3: CA1/PR3 Register Mode Select bit
1 = Enables Capture1
0 = Enables the Period register
TMR3ON: Timer3 On bit
1 = Starts Timer3
0 = Stops Timer3
TMR2ON: Timer2 On bit
This bit controls the incrementing of the TMR2 register. When TMR2:TMR1 form the 16-bit timer
(T16 is set), TMR2ON must be set. This allows the MSB of the timer to increment.
1 = Starts Timer2 (must be enabled if the T16 bit (TCON1<3>) is set)
0 = Stops Timer2
TMR1ON: Timer1 On bit
When T16 is set (in 16-bit Timer mode):
1 = Starts 16-bit TMR2:TMR1
0 = Stops 16-bit TMR2:TMR1
When T16 is clear (in 8-bit Timer mode:
1 = Starts 8-bit Timer1
0 = Stops 8-bit Timer1
CA2OVF
R-0
(The RB3/PWM2 pin ignores the state of the DDRB<3> bit.)
(The RB3/PWM2 pin uses the state of the DDRB<3> bit for data direction.)
(The RB2/PWM1 pin ignores the state of the DDRB<2> bit.)
(The RB2/PWM1 pin uses the state of the DDRB<2> bit for data direction.)
(PR3H/CA1H:PR3L/CA1L is the Capture1 register. Timer3 runs without a period register.)
(PR3H/CA1H:PR3L/CA1L is the Period register for Timer3.)
CA1OVF
R-0
PWM2ON PWM1ON
R/W-0
W = Writable bit
’1’ = Bit is set
R/W-0
CA1/PR3
R/W-0
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
TMR3ON
R/W-0
2000 Microchip Technology Inc.
x = Bit is unknown
TMR2ON TMR1ON
R/W-0
R/W-0
bit 0