ATMEGA323-8PI Atmel, ATMEGA323-8PI Datasheet - Page 110
ATMEGA323-8PI
Manufacturer Part Number
ATMEGA323-8PI
Description
IC AVR MCU 32K 8MHZ IND 40DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA323L-4PC.pdf
(247 pages)
Specifications of ATMEGA323-8PI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA3238PI
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Slave Transmitter Mode
Miscellaneous States
110
ATmega323(L)
In the Slave Transmitter mode, a number of data bytes are transmitted to a Master
Receiver (see Figure 58). The transfer is initialized as in the Slave Receiver mode.
When TWAR and TWCR have been initialized, the Two-wire Serial Interface waits until
it is addressed by its own slave address (or the general call address if enabled) followed
by the Data Direction bit which must be “1” (read) for the Two-wire Serial Interface to
operate in the Slave Transmitter mode. After its own slave address and the read bit
have been received, the Two-wire Serial Interface Interrupt Flag is set and a valid status
code can be read from TWSR. The status code is used to determine the appropriate
software action. The appropriate action to be taken for each status code is detailed in
Table 43. The Slave Transmitter mode may also be entered if arbitration is lost while the
Two-wire Serial Interface is in the Master mode (see state $B0).
If the TWEA bit is reset during a transfer, the Two-wire Serial Interface will transmit the
last byte of the transfer and enter state $C0 or state $C8. the Two-wire Serial Interface
is switched to the not addressed Slave mode, and will ignore the Master if it continues
the transfer. Thus the Master Receiver receives all “1” as serial data. While TWEA is
reset, the Two-wire Serial Interface does not respond to its own slave address. How-
ever, the Two-wire Serial Bus is still monitored and address recognition may resume at
any time by setting TWEA. This implies that the TWEA bit may be used to temporarily
isolate the Two-wire Serial Interface from the Two-wire Serial Bus.
Assembly code illustrating operation of the Slave Receiver mode is given at the end of
the TWI section.
There are two status codes that do not correspond to a defined Two-wire Serial Inter-
face state, see Table 37.
Status $F8 indicates that no relevant information is available because the Two-wire
Serial Interface Interrupt Flag (TWINT) is not set yet. This occurs between other states,
and when the Two-wire Serial Interface is not involved in a serial transfer.
Status $00 indicates that a bus error has occurred during a Two-wire Serial Bus trans-
fer. A bus error occurs when a START or STOP condition occurs at an illegal position in
the format frame. Examples of such illegal positions are during the serial transfer of an
address byte, a data byte or an acknowledge bit. When a bus error occurs, TWINT is
set. To recover from a bus error, the TWSTO Flag must set and TWINT must be cleared
by writing a logic one to it. This causes the Two-wire Serial Interface to enter the not
addressed Slave mode and to clear the TWSTO Flag (no other bits in TWCR are
affected). The SDA and SCL lines are released and no STOP condition is transmitted.
1457G–AVR–09/03
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