ATMEGA323-8PI Atmel, ATMEGA323-8PI Datasheet - Page 70

• Manufacturer Part Number: ATMEGA323-8PI
• Description: IC AVR MCU 32K 8MHZ IND 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA323-8PI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA3238PI

SS Pin Functionality
70
ATmega323(L)
Figure 42. SPI Master-Slave Interconnection
The system is single buffered in the transmit direction and double buffered in the receive
direction. This means that bytes to be transmitted cannot be written to the SPI Data
Register before the entire shift cycle is completed. When receiving data, however, a
received character must be read from the SPI Data Register before the next character
has been completely shifted in. Otherwise, the first byte is lost.
When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is
overridden according to Table 26.
Table 26. SPI Pin Overrides
Note:
When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine
the direction of the SS pin. If SS is configured as an output, the pin is a general output
pin which does not affect the SPI system. If SS is configured as an input, it must be held
high to ensure Master SPI operation. If the SS pin is driven low by peripheral circuitry
when the SPI is configured as a Master with the SS pin defined as an input, the SPI sys-
tem interprets this as another Master selecting the SPI as a Slave and starting to send
data to it. To avoid bus contention, the SPI system takes the following actions:
1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a
2. The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in
Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a
possibility that SS is driven low, the interrupt should always check that the MSTR bit is
still set. If the MSTR bit has been cleared by a Slave Select, it must be set by the user to
re-enable SPI Master mode.
When the SPI is configured as a Slave, the SS pin is always input. When SS is held low,
the SPI is activated, and MISO becomes an output if configured so by the user. All other
pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive,
which means that it will not receive incoming data. Note that the SPI logic will be reset
result of the SPI becoming a Slave, the MOSI and SCK pins become inputs.
SREG is set, the interrupt routine will be executed.
MOSI
MISO
SCK
Pin
CLOCK GENERATOR
SS
1. See “Alternate Functions of Port B” on page 140 for a detailed description of how to
MSB
define the direction of the user defined SPI pins.
8 BIT SHIFT REGISTER
SPI
MASTER
Direction, Master SPI
User Defined
Input
User Defined
User Defined
(1)
LSB
V
MISO
MOSI
SCK
SS
CC
MISO
MOSI
SCK
SS
MSB
Direction, Slave SPI
Input
User Defined
Input
Input
8 BIT SHIFT REGISTER
SLAVE
1457G–AVR–09/03
LSB