ATMEGA162L-8AI Atmel, ATMEGA162L-8AI Datasheet - Page 132

• Manufacturer Part Number: ATMEGA162L-8AI
• Description: IC MCU AVR 16K 3V 8MHZ 44-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162L-8AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

Input Capture Register 1 –
ICR1H and ICR1L
Input Capture Register 3 –
ICR3H and ICR3L
Timer/Counter Interrupt Mask
Register – TIMSK
132
ATmega162(V/U/L)
(1)
The Output Compare Registers contain a 16-bit value that is continuously compared
with the counter value (TCNTn). A match can be used to generate an output compare
interrupt, or to generate a waveform output on the OCnx pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low
bytes are written simultaneously when the CPU writes to these registers, the access is
performed using an 8-bit temporary high byte register (TEMP). This temporary register
is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 107.
The Input Capture is updated with the counter (TCNTn) value each time an event occurs
on the ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1).
The input capture can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes
are read simultaneously when the CPU accesses these registers, the access is per-
formed using an 8-bit temporary high byte register (TEMP). This temporary register is
shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 107.
Note:
• Bit 7 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 overflow interrupt is enabled. The corresponding
Interrupt Vector (See “Interrupts” on page 55.) is executed when the TOV1 flag, located
in TIFR, is set.
• Bit 6 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 55.) is executed when the
OCF1A flag, located in TIFR, is set.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
1. This register contains interrupt control bits for several Timer/Counters, but only
Timer1 bits are described in this section. The remaining bits are described in their
respective Timer sections.
TOIE1
R/W
R/W
R/W
7
0
7
0
7
0
OCIE1A
R/W
R/W
R/W
6
0
6
0
6
0
OCIE1B
R/W
R/W
R/W
5
0
5
0
5
0
OCIE2
R/W
R/W
R/W
4
0
4
0
4
0
ICR1[15:8]
ICR3[15:8]
ICR1[7:0]
ICR3[7:0]
TICIE1
R/W
R/W
R/W
3
0
3
0
3
0
TOIE2
R/W
R/W
R/W
2
0
2
0
2
0
TOIE0
R/W
R/W
R/W
1
0
1
0
1
0
OCIE0
R/W
R/W
R/W
0
0
0
0
0
0
2513C–AVR–09/02
ICR1H
ICR3H
ICR1L
ICR3L
TIMSK