ATMEGA162L-8AI Atmel, ATMEGA162L-8AI Datasheet - Page 39

• Manufacturer Part Number: ATMEGA162L-8AI
• Description: IC MCU AVR 16K 3V 8MHZ 44-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162L-8AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

Clock output buffer
Timer/Counter Oscillator
System Clock Prescaler
Clock Prescale Register –
CLKPR
2513C–AVR–09/02
When the CKOUT Fuse is programmed, the system clock will be output on PortB 0. This
mode is suitable when chip clock is used to drive other circuits on the system. The clock
will be output also during Reset and the normal operation of PortB will be overridden
when the fuse is programmed. Any clock sources, including Internal RC Oscillator, can
be selected when PortB 0 serves as clock output.
If the system clock prescaler is used, it is the divided system clock that is output when
the CKOUT Fuse is programmed. See “System Clock Prescaler” on page 39. for a
description of the system clock prescaler.
For AVR microcontrollers with Timer/Counter Oscillator pins (TOSC1 and TOSC2), the
crystal is connected directly between the pins. The Oscillator provides internal capaci-
tors on TOSC1 and TOSC2, thereby removing the need for external capacitors. The
internal capacitors have a nominal value of 10 pF. The Oscillator is optimized for use
with a 32.768 kHz watch crystal. Applying an external clock source to TOSC1 is not
recommended.
The ATmega162 system clock can be divided by setting the Clock Prescale Register –
CLKPR. This feature can be used to decrease power consumption when the require-
ment for processing power is low. This can be used with all clock source options, and it
will affect the clock frequency of the CPU and all synchronous peripherals. clk
and clk
of clk
clocked synchronously.
• Bit 7 – CPCE: Clock Prescaler Change Enable
The CPCE bit must be written to logic one to enable change of the CLKPS bits. CPCE is
cleared by hardware four cycles after it is written or when CLKPS is written. Setting the
CPCE bit will disable interrupts, as explained in the CLKPS description below.
• Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal
system clock. These bits can be written run-time to vary the clock frequency to suit the
application requirements. As the divider divides the master clock input to the MCU, the
speed of all synchronous peripherals is reduced when a division factor is used. The divi-
sion factors are given in Table 15.
To avoid unintentional changes of clock frequency, a special write procedure must be
followed to change the CLKPS bits:
1. Write the Clock Prescaler Change Enable (CPCE) bit to one and all other bits in
2. Within four cycles, write the desired value to CLKPS while writing a zero to
Caution: An interrupt between step 1 and step 2 will make the timed sequence fail. It is
recommended to have the Global Interrupt Flag cleared during these steps to avoid this
problem.
Bit
Read/Write
Initial Value
CLKPR to zero.
CPCE.
ASY
FLASH
(asynchronously Timer/Counter) only will be scaled if the Timer/Counter is
are divided by a factor as shown in Table 15. Note that the clock frequency
CPCE
R/W
7
0
R
6
–
0
R
5
–
0
R
4
0
–
CLKPS3
R/W
3
ATmega162(V/U/L)
CLKPS2
See Bit Description
R/W
2
CLKPS1
R/W
1
CLKPS0
R/W
0
I/O
, clk
CLKPR
CPU
39
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