ATMEGA162L-8AI Atmel, ATMEGA162L-8AI Datasheet - Page 59

• Manufacturer Part Number: ATMEGA162L-8AI
• Description: IC MCU AVR 16K 3V 8MHZ 44-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162L-8AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

Moving Interrupts Between
Application and Boot Space
General Interrupt Control
Register – GICR
2513C–AVR–09/02
When the BOOTRST Fuse is programmed, the boot section size set to 2K bytes and the
IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical
and general program setup for the Reset and Interrupt Vector Addresses is:
The General Interrupt Control Register controls the placement of the Interrupt Vector
table.
• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the
Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the begin-
ning of the Boot Loader section of the Flash. The actual address of the start of the Boot
Flash section is determined by the BOOTSZ Fuses. Refer to the section “Boot Loader
Support – Read-While-Write Self-programming” on page 214 for details. To avoid unin-
tentional changes of Interrupt Vector tables, a special write procedure must be followed
to change the IVSEL bit:
1. Write the Interrupt Vector Change Enable (IVCE) bit to one.
2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are
disabled in the cycle IVCE is set, and they remain disabled until after the instruction fol-
lowing the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four
cycles. The I-bit in the Status Register is unaffected by the automatic disabling.
Note:
• Bit 0 – IVCE: Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is
cleared by hardware four cycles after it is written or when IVSEL is written. Setting the
Bit
Read/Write
Initial Value
Address
.org 0x1C00
0x1C00
0x1C02
0x1C04
...
0x1C36
;
0x1C38
0x1C39
0x1C3A
0x1C3B
0x1C3C
0x1C3D
If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is pro-
grammed, interrupts are disabled while executing from the Application section. If
Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is pro-
gramed, interrupts are disabled while executing from the Boot Loader section. Refer to
the section “Boot Loader Support – Read-While-Write Self-programming” on page 214
for details on Boot Lock bits.
Labels
....
RESET:
INT1
R/W
7
0
INT0
R/W
6
0
Code
jmp
jmp
jmp
..
jmp
ldi
out
ldi
out
sei
<instr>
RESET
EXT_INT0
EXT_INT1
SPM_RDY
r16,high(RAMEND) ; Main program start
SPH,r16
r16,low(RAMEND)
SPL,r16
INT2
R/W
5
0
xxx
PCIE1
R/W
4
0
PCIE0
R/W
Comments
; Reset handler
; IRQ0 Handler
; IRQ1 Handler
;
; Store Program Memory Ready Handler
; Set stack pointer to top of RAM
; Enable interrupts
3
0
ATmega162(V/U/L)
R
2
–
0
IVSEL
R/W
1
0
IVCE
R/W
0
0
GICR
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