IC 8051 MCU FLASH 64K 44PLCC

AT89C51RD2-SLSIM

Manufacturer Part NumberAT89C51RD2-SLSIM
DescriptionIC 8051 MCU FLASH 64K 44PLCC
ManufacturerAtmel
Series89C
AT89C51RD2-SLSIM datasheet
 

Specifications of AT89C51RD2-SLSIM

Core Processor8051Core Size8-Bit
Speed60MHzConnectivitySPI, UART/USART
PeripheralsPOR, PWM, WDTNumber Of I /o34
Program Memory Size64KB (64K x 8)Program Memory TypeFLASH
Ram Size2K x 8Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 V
Oscillator TypeExternalOperating Temperature-40°C ~ 85°C
Package / Case44-PLCCFor Use WithAT89STK-11 - KIT STARTER FOR AT89C51RX2
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantEeprom Size-
Data Converters-  
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Features
80C52 Compatible
– 8051 Instruction Compatible
– Six 8-bit I/O Ports (64 Pins or 68 Pins Versions)
– Four 8-bit I/O Ports (44 Pins Version)
– Three 16-bit Timer/Counters
– 256 Bytes Scratch Pad RAM
– 9 Interrupt Sources with 4 Priority Levels
Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply
ISP (In-System Programming) Using Standard V
2048 Bytes Boot ROM Contains Low Level Flash Programming Routines and a Default
Serial Loader
High-speed Architecture
– In Standard Mode:
• 40 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
• 60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
– In X2 mode (6 Clocks/machine cycle)
• 20 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
• 30 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
64K Bytes On-chip Flash Program/Data Memory
– Byte and Page (128 Bytes) Erase and Write
– 100k Write Cycles
On-chip 1792 bytes Expanded RAM (XRAM)
– Software Selectable Size (0, 256, 512, 768, 1024, 1792 Bytes)
– 768 Bytes Selected at Reset for T89C51RD2 Compatibility
On-chip 2048 Bytes EEPROM Block for Data Storage (AT89C51ED2 Only)
100K Write Cycles
Dual Data Pointer
Variable Length MOVX for Slow RAM/Peripherals
Improved X2 Mode with Independent Selection for CPU and Each Peripheral
Keyboard Interrupt Interface on Port 1
SPI Interface (Master/Slave Mode)
8-bit Clock Prescaler
16-bit Programmable Counter Array
– High Speed Output
– Compare/Capture
– Pulse Width Modulator
– Watchdog Timer Capabilities
Asynchronous Port Reset
Full-duplex Enhanced UART with Dedicated Internal Baud Rate Generator
Low EMI (Inhibit ALE)
Hardware Watchdog Timer (One-time Enabled with Reset-Out), Power-off Flag
Power Control Modes: Idle Mode, Power-down Mode
Single Range Power Supply: 2.7V to 5.5V
Industrial Temperature Range (-40 to +85°C)
Packages: PLCC44, VQFP44, PLCC68, VQFP64
Power Supply
CC
8-bit Flash
Microcontroller
AT89C51RD2
AT89C51ED2

AT89C51RD2-SLSIM Summary of contents

  • Page 1

    ... Hardware Watchdog Timer (One-time Enabled with Reset-Out), Power-off Flag • Power Control Modes: Idle Mode, Power-down Mode • Single Range Power Supply: 2.7V to 5.5V • Industrial Temperature Range (-40 to +85°C) • Packages: PLCC44, VQFP44, PLCC68, VQFP64 Power Supply CC 8-bit Flash Microcontroller AT89C51RD2 AT89C51ED2 ...

  • Page 2

    ... ISP capability or with software. The programming voltage is internally generated from the standard V The AT89C51RD2/ED2 retains all of the features of the Atmel 80C52 with 256 bytes of internal RAM, a 9-source 4-level interrupt controller and three timer/counters. The AT89C51ED2 pro- vides 2048 bytes of EEPROM for nonvolatile data storage. ...

  • Page 3

    ... C51 CORE IB-bus Parallel I/O Ports & Timer 0 INT External Bus Timer 1 Ctrl Port 0 Port 1 Port 2 Port 3 (2) (2) (2) (2) (1): Alternate function of Port 1 (2): Alternate function of Port 3 AT89C51RD2/ED2 (1) (1) (1) (1) (1) EEPROM* Watch PCA Timer2 Keyboard -dog (AT89C51ED2) BOOT Regulator SPI ...

  • Page 4

    ... SFR Mapping The Special Function Registers (SFRs) of the AT89C51RD2/ED2 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP • I/O port registers: P0, P1, P2, P3, PI2 • Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H • ...

  • Page 5

    ... PPCL PT2L PLS - - - - - - - - TF1 TR1 TF0 TR0 GATE1 C/T1# M11 M01 - - - - TF2 EXF2 RCLK TCLK - - - - AT89C51RD2/ED2 ET1 EX1 ET0 EX0 - ESPI KBD PT1H PX1H PT0H PX0H PT1L PX1L PT0L PX0L - SPIH KBDH - SPIL KBDL IE1 IT1 IE0 IT0 GATE0 C/T0# M10 ...

  • Page 6

    ... BDRCON 9Bh Baud Rate Control BRL 9Ah Baud Rate Reload Table 3-8. SPI Controller SFRs Mnemonic Add Name SPCON C3h SPI Control SPSTA C4h SPI Status SPDAT C5h SPI Data AT89C51RD2/ED2 CCF4 CIDL WDTE ECOM0 CAPP0 CAPN0 ECOM1 CAPP1 CAPN1 ECOM2 ...

  • Page 7

    ... X000 0000 X000 0000 X000 0000 EECON xxxx xx00 RCAP2L RCAP2H TL2 0000 0000 0000 0000 0000 0000 SPCON SPSTA 0001 0100 0000 0000 IPL1 IPH1 XXXX X000 XXXX X000 AT89C51RD2/ED2 KBLS4 KBLS3 KBLS2 KBE4 KBE3 KBE2 KBF4 KBF3 KBF2 5/D ...

  • Page 8

    ... XXXX XXXX P1 90h 1111 1111 TCON TMOD 88h 0000 0000 0000 0000 P0 SP 80h 0000 0111 1111 1111 0/8 1/9 AT89C51RD2/ED2 8 AUXR1 0XXX X0X0 BRL BDRCON KBLS 0000 0000 XXX0 0000 0000 0000 TL0 TL1 TH0 0000 0000 0000 0000 0000 0000 ...

  • Page 9

    ... NIC* PLCC44 P3.1/TxD 13 P3.2/INT0 14 P3.3/INT1 15 P3.4/T0 16 P3.5/ RST 4 P3.0/RxD 5 AT89C51RD2/ED2 NIC* 6 VQFP44 1.4 P3.1/TxD 7 8 P3.2/INT0 P3.3/INT1 9 P3.4/T0 10 P3.5/ AT89C51RD2/ED2 39 P0.4/AD4 38 P0.5/AD5 37 P0.6/AD6 36 P0.7/AD7 NIC* 33 ALE/PROG 32 PSEN 31 P2.7/A15 30 P2.6/A14 29 P2.5/A13 P0.4/AD4 33 32 P0.5/AD5 31 P0.6/AD6 30 P0.7/AD7 NIC* 27 ALE/PROG 26 PSEN 25 P2.7/A15 24 P2.6/A14 23 P2.5/A13 ...

  • Page 10

    ... P5.5 1 P0.3/AD3 2 P0.2/AD2 3 P5.6 4 P0.1/AD1 5 P0.0/AD0 6 P5.7 7 AT89C51ED2 VCC 8 NIC 9 P1.0/T2 10 P4.0 11 P1.1/T2EX P1.2/ECI 13 P1.3/CEX0 14 P4.1 15 P1.4/CEX1 16 AT89C51RD2/ED2 10 P5.5 10 P0.3/AD3 11 P0.2/AD2 12 P5.6 13 P0.1/AD1 14 P0.0/AD0 15 P5.7 16 VCC 17 NIC 18 P1.0/T2 19 P4.0 20 P1.1/T2EX P1.2/ECI 22 P1.3/CEX0 23 P4.1 24 P1.4/CEX1 25 P4 P2.4/A12 47 P2.3/A11 46 P4.7 45 P2.2/A10 44 P2.1/A9 43 P2.0/ ...

  • Page 11

    ... As inputs, Port 1 pins that are externally 28, 29 19, 20 pulled low will source current because of the internal pull-ups. Port 1 also receives the low-order address byte during memory programming and verification. Alternate functions for AT89C51RD2/ED2 Port 1 include I/O P1.0: Input/Output I/O T2 (P1 ...

  • Page 12

    ... P4 P5 RST 10 4 AT89C51RD2/ED2 12 Type PLCC68 VQFP64 Name and Function 29 20 I/O P1.7: Input/Output: I/O CEX4: Capture/Compare External I/O for PCA module 4 I/O MOSI: SPI Master Output Slave Input line When SPI is in master mode, MOSI outputs data to the slave peripheral. ...

  • Page 13

    ... PSEN is not activated during fetches from internal program memory External Access Enable: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to FFFFH. If security level 1 is programmed, EA will be internally latched on Reset. AT89C51RD2/ED2 13 ...

  • Page 14

    ... Port Types AT89C51RD2/ED2 I/O ports (P1, P2, P3, P4, P5) implement the quasi-bidirectional output that is common on the 80C51 and most of its derivatives. This output type can be used as both an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic high weakly driven, allowing an external device to pull the pin low. When the pin is pulled low driven strongly and able to sink a fairly large current ...

  • Page 15

    ... Set by software for general-purpose usage. Power-down Mode bit 1 PD Cleared by hardware when reset occurs. Set to enter power-down mode. Idle Mode bit 0 IDL Cleared by hardware when interrupt or reset occurs. Set to enter idle mode. AT89C51RD2/ED2 CKRL3 CKRL2 GF1 GF0 rises from 0 to its nominal voltage. Can also be ...

  • Page 16

    ... CKRL = 00h: minimum frequency F F • CKRL = FFh: maximum frequency CLK CPU In X2 Mode, for CKRL<>0xFF CPU In X1 Mode, for CKRL<>0xFF then CPU AT89C51RD2/ED2 16 Reload CKRL 1 8-bit 0 Prescaler-Divider X2 CKCON0 = F CLK CPU CLK PERIPH = /1020 (Standard Mode) CLK CPU CLK PERIPH ...

  • Page 17

    ... Some enhanced features are also located in the UART and the Timer 2 7.1 X2 Feature The AT89C51RD2/ED2 core needs only 6 clock periods per machine cycle. This feature called ‘X2’ provides the following advantages: • Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power. ...

  • Page 18

    ... These bits are active only in X2 mode. Table 7-1. CKCON0 - Clock Control Register (8Fh Bit Number 7 6 AT89C51RD2/ED2 18 Clock Generation Diagram XTAL1:2 2 XTAL1 FXTAL CKCON0 F OSC ...

  • Page 19

    ... Set to select 6 clock periods per machine cycle (X2 mode) and to enable the individual peripherals’X2’ bits. Programmed by hardware after Power-up regarding Hardware Security Byte (HSB), Default setting cleared. CKCON1 Register Bit Mnemonic Description - Reserved - Reserved - Reserved - Reserved - Reserved AT89C51RD2/ED2 SPIX2 19 ...

  • Page 20

    ... Bit Number Reset Value = XXXX XXX0b Not bit addressable AT89C51RD2/ED2 20 Bit Mnemonic Description - Reserved - Reserved SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). SPIX2 Clear to select 6 clock periods per peripheral clock cycle. ...

  • Page 21

    ... The value read from this bit is indeterminate. Do not set this bit. GF3 This bit is a general-purpose user flag. 0 Always cleared Reserved - The value read from this bit is indeterminate. Do not set this bit. Data Pointer Selection DPS Cleared to select DPTR0. Set to select DPTR1. AT89C51RD2/ED2 External Data Memory GF3 0 - (1) 0 DPS 21 ...

  • Page 22

    ... DPS is '0' or '1' on entry. Observe that without the last instruc- tion (INC AUXR1), the routine will exit with DPS in the opposite state. AT89C51RD2/ED2 22 1. Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3. ...

  • Page 23

    ... The AT89C51RD2/ED2 provides additional on-chip random access memory (RAM) space for increased data parameter handling and high level language usage. AT89C51RD2/ED2 device haS expanded RAM in external data space configurable up to 1792 bytes (see The AT89C51RD2/ED2 internal data memory is mapped into four separate segments. ...

  • Page 24

    ... This is useful to access external slow peripherals. 9.1 Registers Table 9-1. AUXR - Auxiliary Register (8Eh) 7 DPU Bit Number AT89C51RD2/ED2 24 AUXR Register XRS2 Bit Mnemonic Description Disable Weak Pull-up DPU Cleared by software to activate the permanent weak pull-up (default) Set by software to disable the weak pull-up (reduce power consumption) ...

  • Page 25

    ... Set to access external memory. Programmed by hardware after Power-up regarding Hardware Security Byte (HSB), default setting, XRAM selected. ALE Output bit Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1 mode is used). (default) Set, ALE is active only during a MOVX or MOVC instruction is used. AT89C51RD2/ED2 25 ...

  • Page 26

    ... The Reset input can be used to force a reset pulse longer than the internal reset controlled by the Power Monitor. RST input has a pull-down resistor allowing power-on reset by simply con- necting an external capacitor to V characteristics are discussed in the Section “DC Characteristics” of the AT89C51RD2/ED2 datasheet. Figure 10-2. Reset Circuitry and Power-On Reset 10 ...

  • Page 27

    ... Figure 10-3. Recommended Reset Output Schematic 4235K–8051–05/08 VDD + RST VDD 1K RST VSS AT89C51RD2/ED2 AT89C51XD2 To other on-board circuitry 27 ...

  • Page 28

    ... The POR/PFD function monitors the internal power-supply of the CPU core memories and the peripherals, and if needed, suspends their activity when the internal power supply falls below a safety threshold. This is achieved by applying an internal reset to them. By generating the Reset the Power Monitor insures a correct start up when AT89C51RD2/ED2 is powered up. 11.1 ...

  • Page 29

    ... The internal reset will remain asserted until the Xtal1 levels are above and below VIH and VIL. Further more. An internal counter will count 1024 clock periods before the reset is de-asserted. If the internal power supply falls below a safety level, a reset is immediately asserted. . 4235K–8051–05/08 AT89C51RD2/ED2 t 29 ...

  • Page 30

    ... Timer 2 The Timer 2 in the AT89C51RD2/ED2 is the standard C52 Timer 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 are cascaded con- trolled by T2CON (Table 12-1) and T2MOD (Table 12-2) registers. Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects F tion) as the timer clock input ...

  • Page 31

    ... COUNTING RELOAD VALUE) (UP COUNTING RELOAD VALUE) F CLKPERIPH = -------------------------------------------------------------------------------------------- - 4 65536 RCAP2H RCAP2L × ( – MHz (F /4). The generated clock signal is brought out to T2 pin ) CLK PERIPH AT89C51RD2/ED2 TR2 C/T2 T2CON T2CON T2EX: If DCEN = FFh FFh If DCEN = DOWN (8-bit) (8-bit) If DCEN = 0, up counting TOGGLE ...

  • Page 32

    ... RCAP2H and RCAP2L registers. Figure 12-2. Clock-out Mode C/ 12.3 Registers Table 12-1. T2CON - Timer 2 Control Register (C8h) 7 TF2 AT89C51RD2/ED2 32 :6 FCLK PERIPH T2 T2EX T2CON T2CON Register 6 ...

  • Page 33

    ... Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode. Timer 2 Capture/Reload bit If RCLK = 1 or TCLK = 1, CP/RL2# is ignored and timer is forced to auto-reload on Timer 2 overflow. CP/RL2# Cleared to auto-reload on Timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2 = 1. AT89C51RD2/ED2 ). CLK PERIPH 33 ...

  • Page 34

    ... Table 12-2. T2MOD - Timer 2 Mode Control Register (C9h Bit Number Reset Value = XXXX XX00b Not bit addressable AT89C51RD2/ED2 34 T2MOD Register Bit Mnemonic Description Reserved - The value read from this bit is indeterminate. Do not set this bit. Reserved - The value read from this bit is indeterminate. Do not set this bit. ...

  • Page 35

    ... CLK PERIPH ÷ ) CLK PERIPH PCA Component 16-bit Counter 16-bit Module 0 16-bit Module 1 16-bit Module 2 16-bit Module 3 peripheral clock frequency (F CLK PERIPH peripheral clock frequency (F CLK PERIPH AT89C51RD2/ED2 6 2 External I/O Pin P1.2/ECI P1.3/CEX0 P1.4/CEX1 P1.5/CEX2 P1.6/CEX3 ) ) 35 ...

  • Page 36

    ... The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR set when the PCA timer overflows. Figure 13-1. PCA Timer/Counter F /6 CLK PERIPH F /2 CLK PERIPH T0 OVF P1.2 Idle AT89C51RD2/ED2 Bit Up Counter CIDL WDTE CPS1 CPS0 CF CR CCF4 CCF3 CCF2 CCF1 CCF0 To PCA Modules ...

  • Page 37

    ... Internal clock F CPS0 1 0 Timer 0 Overflow 1 1 External clock at ECI/P1.2 pin (max rate = F PCA Enable Counter Overflow Interrupt ECF Cleared to disable CF bit in CCON to inhibit an interrupt. Set to enable CF bit in CCON to generate an interrupt. AT89C51RD2/ED2 CPS1 CPS0 /6 CLK PERIPH /2 CLK PERIPH /4) CLK PERIPH 0 ...

  • Page 38

    ... Number Reset Value = 00X0 0000b Bit addressable The watchdog timer function is implemented in Module 4 (See Figure 13-4). The PCA interrupt system is shown in Figure 13-2. AT89C51RD2/ED2 38 CCON Register CCF4 Bit Mnemonic Description PCA Counter Overflow flag Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is CF set ...

  • Page 39

    ... If both bits are set both edges will be enabled and a capture will occur for either transition. • The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function. 4235K–8051–05/ CCF4 CCF3 CCF2 CCF1 CCF0 ECF ECCFn CCAPMn.0 AT89C51RD2/ED2 CCON 0xD8 To Interrupt Priority Decoder IEN0.6 IEN0 ...

  • Page 40

    ... CCAPM3 - PCA Module 3 Compare/Capture Control Register (0DDh) CCAPM4 - PCA Module 4 Compare/Capture Control Register (0DEh Bit Number Reset Value = X000 0000b Not bit addressable AT89C51RD2/ED2 40 CCAPMn Registers ( ECOMn CAPPn CAPNn Bit Mnemonic Description Reserved - The value read from this bit is indeterminate. Do not set this bit. Enable Comparator ECOMn Cleared to disable the comparator function ...

  • Page 41

    ... X CCAPnH Registers ( Bit Mnemonic Description PCA Module n Compare/Capture Control - CCAPnH Value AT89C51RD2/ED2 PWMm ECCFn Module Function Operation 16-bit capture by a positive-edge 0 X trigger on CEXn 16-bit capture by a negative trigger CEXn 0 X 16-bit capture by a transition on CEXn 0 X 16-bit Software Timer/Compare mode. ...

  • Page 42

    ... CH - PCA Counter Register High (0F9h Bit Number Reset Value = 0000 0000b Not bit addressable Table 13- PCA Counter Register Low (0E9h Bit Number Reset Value = 0000 0000b Not bit addressable AT89C51RD2/ED2 42 CCAPnL Registers ( Bit Mnemonic Description PCA Module n Compare/Capture Control - CCAPnL Value CH Register 6 ...

  • Page 43

    ... CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (See Figure 13-4). 4235K–8051–05/08 CCF4 CCF3 CCF2 CCF1 CCF0 Capture CAPPn CAPNn MATn TOGn PWMn ECCFn AT89C51RD2/ED2 CCON 0xD8 PCA IT PCA Counter/Timer CH CL ...

  • Page 44

    ... PCA counter and the modules capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR must be set (See Figure 13-5). A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit. AT89C51RD2/ED2 44 CF CCF4 ...

  • Page 45

    ... The PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode. 4235K–8051–05/ CCF4 CCF3 CCF2 CCF1 CCF0 CCAPnH CCAPnL Match 16 bit comparator CH CL PCA counter/timer ECO Mn CAPPn CAPNn MATn TOGn PWMn ECCFn AT89C51RD2/ED2 CCON 0xD8 PCA IT CEXn CCAPMn 0xDA to 0xDE 45 ...

  • Page 46

    ... Periodically change the compare value so it will never match the PCA timer. 2. Periodically change the PCA timer value so it will never match the compare values. 3. Disable the watchdog by clearing the WDTE bit before a match occurs and then re- enable it. AT89C51RD2/ED2 46 CCAPnH Overflow ...

  • Page 47

    ... Remember, the PCA timer is the time base for all modules; changing the time base for other modules would not be a good idea. Thus, in most applications the first solution is the best option. This watchdog timer won’t generate a reset out on the reset pin. 4235K–8051–05/08 AT89C51RD2/ED2 47 ...

  • Page 48

    ... Serial I/O Port The serial I/O port in the AT89C51RD2/ED2 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as a Univer- sal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud ...

  • Page 49

    ... FE SMOD0=1 The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i. e. setting SM2 bit in SCON register in mode 0 has no effect). SADDR0101 0110b SADEN1111 1100b Given0101 01XXb SADEN1111 1010b Given1111 0X0Xb SADEN1111 1001b Given1111 0XX1b AT89C51RD2/ED2 Data byte Ninth bit Stop ...

  • Page 50

    ... On reset, the SADDR and SADEN registers are initialized to 00h the given and broadcast addresses are XXXX XXXXb (all don’t-care bits). This ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition. AT89C51RD2/ED2 50 SADEN1111 1101b Given1111 00X1b ...

  • Page 51

    ... The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON registers. Figure 14-4. Baud Rate Selection 4235K–8051–05/08 SADEN Register SADDR Register TIMER1 TIMER_BRG_RX 0 TIMER2 1 RCLK INT_BRG TIMER1 TIMER_BRG_TX 0 TIMER2 1 TCLK INT_BRG AT89C51RD2/ED2 Clock 1 RBCK Clock TBCK ...

  • Page 52

    ... BRL reload value, the value of SPD bit (Speed Mode) in BDRCON register and the value of the SMOD1 bit in PCON register. Figure 14-5. Internal Baud Rate • The baud rate for UART is token by formula: Baud_Rate = BRL = 256 - AT89C51RD2/ED2 52 Baud Rate Selection Table UART RCLK TBCK (T2CON) ...

  • Page 53

    ... Set by hardware at the end of the 8th bit time in mode the beginning of the stop bit in the other modes. Receive Interrupt flag Clear to acknowledge interrupt. RI Set by hardware at the end of the 8th bit time in mode 0, see Figure 14-2. and Figure 14-3. in the other modes. AT89C51RD2/ED2 TB8 RB8 TI ...

  • Page 54

    ... Table 14-7. SADEN - Slave Address Mask Register for UART (B9h) 7 Reset Value = 0000 0000b Table 14-8. SADDR - Slave Address Register for UART (A9h) 7 Reset Value = 0000 0000b AT89C51RD2/ED2 54 Example of Computed Value When X2=1, SMOD1=1, SPD 16. 384 MHz OSC BRL 247 238 ...

  • Page 55

    ... Table 14-9. SBUF - Serial Buffer Register for UART (99h) 7 Reset Value = XXXX XXXXb Table 14-10. BRL Register BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah) 7 Reset Value = 0000 0000b 4235K–8051–05/08 SBUF Register AT89C51RD2/ED2 ...

  • Page 56

    ... T2CON - Timer 2 Control Register (C8h) 7 TF2 Bit Number Reset Value = 0000 0000b Bit addressable AT89C51RD2/ED2 EXF2 RCLK TCLK Bit Mnemonic Timer 2 overflow Flag TF2 Must be cleared by software. Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0. Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1 ...

  • Page 57

    ... Cleared by user for general purpose usage. Set by user for general purpose usage. Power-Down mode bit PD Cleared by hardware when reset occurs. Set to enter power-down mode. Idle mode bit IDL Cleared by hardware when interrupt or reset occurs. Set to enter idle mode. AT89C51RD2/ED2 GF1 GF0 PD Description 0 IDL ...

  • Page 58

    ... Table 14-13. BDRCON Register BDRCON - Baud Rate Control Register (9Bh Bit Number Reset Value = XXX0 0000b Not bit addressable AT89C51RD2/ED2 BRR Bit Mnemonic Description Reserved - The value read from this bit is indeterminate. Do not set this bit Reserved - The value read from this bit is indeterminate. Do not set this bit ...

  • Page 59

    ... Keyboard Interface The AT89C51RD2/ED2 implements a keyboard interface allowing the connection matrix keyboard based on 8 inputs with programmable interrupt capability on both high or low level. These inputs are available as alternate function of P1 and allow to exit from idle and power-down modes. The keyboard interfaces with the C51 core through 3 special function registers: KBLS, the Key- board Level Selection register (Table 15-3), KBE, the Keyboard interrupt Enable register (Table 15-2), and KBF, the Keyboard Flag register (Table 15-1) ...

  • Page 60

    ... KBF7 Bit Number Reset Value = 0000 0000b This register is read only access, all flags are automatically cleared by reading the register. AT89C51RD2/ED2 60 KBF Register KBF6 KBF5 KBF4 Bit Mnemonic Description Keyboard line 7 flag Set by hardware when the Port line 7 detects a programmed level. It generates a KBF7 Keyboard interrupt request if the KBKBIE ...

  • Page 61

    ... Keyboard line 1 Enable bit KBE1 Cleared to enable standard I/O pin. Set to enable KBF.1 bit in KBF register to generate an interrupt request. Keyboard line 0 Enable bit KBE0 Cleared to enable standard I/O pin. Set to enable KBF.0 bit in KBF register to generate an interrupt request. AT89C51RD2/ED2 KBE3 KBE2 KBE1 0 ...

  • Page 62

    ... Table 15-3. KBLS-Keyboard Level Selector Register (9Ch) 7 KBLS7 Bit Number Reset Value = 0000 0000b AT89C51RD2/ED2 62 KBLS Register KBLS6 KBLS5 KBLS4 Bit Mnemonic Description Keyboard line 7 Level Selection bit KBLS7 Cleared to enable a low level detection on Port line 7. Set to enable a high level detection on Port line 7. ...

  • Page 63

    ... Slave, and an input signal to the Master. A Byte (8-bit word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last. 4235K–8051–05/08 shows a typical SPI bus configuration using one Master controller and many Slave MISO MOSI SCK SS VDD Master Slave 4 AT89C51RD2/ED2 Slave 1 Slave 3 Slave 2 63 ...

  • Page 64

    ... AT89C51RD2/ED2 Clearing SSDIS control bit does not clear MODF. 2. Special care should be taken not to set SSDIS control bit when CPHA = ’0’ because in this mode, the SS is used to start the transmission. gives the different clock rates selected by SPR2:SPR1:SPR0. SPI Master Baud Rate Selection ...

  • Page 65

    ... SPI Module. FCLK PERIPH /4 Clock /8 /16 Divider /32 /64 /128 Clock Select SPR2 SPEN SSDIS MSTR SPI Interrupt Request AT89C51RD2/ED2 Internal Bus SPDAT Shift Register Receive Data Register Pin Control Logic Clock M Logic ...

  • Page 66

    ... CPHA defines the edges on which the input data are sampled and the edges on which the out- put data are shifted (Figure 16-4 and Figure 16-5). The clock phase and polarity should be identical for the Master SPI device and the communicating Slave device AT89C51RD2/ED2 66 MISO 8-bit Shift register MOSI SPI SCK ...

  • Page 67

    ... MSB bit6 bit5 bit4 bit3 Byte 1 Byte 2 Figure 16-4, the first SCK edge is the MSB capture strobe. Therefore, the Slave shows an SPI transmission in which CPHA is ’1’. In this case, the Master begins AT89C51RD2/ED2 bit2 bit1 LSB bit2 bit1 LSB 6 7 ...

  • Page 68

    ... SPI state machine). 16.3.4 Interrupts Two SPI status flags can generate a CPU interrupt requests: Table 16-2. Flag SPIF (SP data transfer) MODF (Mode Fault) AT89C51RD2/ED2 68 SPI Interrupts Request SPI Transmitter Interrupt request SPI Receiver/Error Interrupt Request (if SSDIS = ’0’) 4235K–8051–05/08 ...

  • Page 69

    ... SS Disable Cleared to enable SS in both Master and Slave modes. SSDIS Set to disable SS in both Master and Slave modes. In Slave mode, this bit has no effect if CPHA =’0’. When SSDIS is set, no MODF interrupt request . is generated AT89C51RD2/ED2 SPI CPU Interrupt Request CPOL CPHA ...

  • Page 70

    ... Inconsistent logic level on SS pin (mode fault error) Table 16-4 Table 16-4. SPSTA - Serial Peripheral Status and Control register (0C4H) 7 SPIF Bit Number 7 6 AT89C51RD2/ED2 70 Bit Mnemonic Description Serial Peripheral Master MSTR Cleared to configure the SPI as a Slave. Set to configure the SPI as a Master. Clock Polarity CPOL Cleared to have the SCK set to ’ ...

  • Page 71

    ... The value read from this bit is indeterminate. Do not set this bit. Reserved - The value read from this bit is indeterminate. Do not set this bit. Reserved - The value read from this bit is indeterminate. Do not set this bit. (Table 16- read/write buffer for the receive data regis- SPDAT Register AT89C51RD2/ED2 ...

  • Page 72

    ... Interrupt System The AT89C51RD2/ED2 has a total of 9 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt, Keyboard interrupt and the PCA global interrupt. These interrupts are shown in Figure 17-1. Figure 17-1. Interrupt Control System ...

  • Page 73

    ... Interrupt Sources and Vector Addresses Polling Priority Interrupt Source 0 Reset 1 INT0 2 Timer 0 3 INT1 4 Timer 1 6 UART 7 Timer 2 5 PCA 8 Keyboard SPI AT89C51RD2/ED2 Interrupt Level Priority 0 0 (Lowest (Highest) Interrupt Request IE0 TF0 IE1 IF1 RI+TI TF2+EXF2 CF + CCFn ( KBDIT - SPIIT Vector Address 0000h ...

  • Page 74

    ... Table 17-3. IEN0 - Interrupt Enable Register (A8h Bit Number Reset Value = 0000 0000b Bit addressable AT89C51RD2/ED2 74 IENO Register ET2 ES Bit Mnemonic Description Enable All interrupt bit EA Cleared to disable all interrupts. Set to enable all interrupts. PCA interrupt enable bit EC Cleared to disable. Set to enable. ...

  • Page 75

    ... Refer to PT1H for priority level. External interrupt 1 Priority bit PX1L Refer to PX1H for priority level. Timer 0 overflow interrupt Priority bit PT0L Refer to PT0H for priority level. External interrupt 0 Priority bit PX0L Refer to PX0H for priority level. AT89C51RD2/ED2 PT1L PX1L PT0L 0 PX0L 75 ...

  • Page 76

    ... IPH0 - Interrupt Priority High Register (B7h Bit Number Reset Value = X000 0000b Not bit addressable AT89C51RD2/ED2 76 IPH0 Register PPCH PT2H PSH Bit Mnemonic Description Reserved - The value read from this bit is indeterminate. Do not set this bit. PCA interrupt Priority high bit. ...

  • Page 77

    ... IEN1 Register Bit Mnemonic Description - Reserved - Reserved - Reserved - Reserved - Reserved SPI interrupt Enable bit Cleared to disable SPI interrupt. ESPI Set to enable SPI interrupt. Reserved Keyboard interrupt Enable bit KBD Cleared to disable keyboard interrupt. Set to enable keyboard interrupt. AT89C51RD2/ED2 ESPI - 0 KBD 77 ...

  • Page 78

    ... Table 17-7. IPL1 - Interrupt Priority Register (B2h Bit Number Reset Value = XXXX X000b Bit addressable AT89C51RD2/ED2 78 IPL1 Register Bit Mnemonic Description Reserved - The value read from this bit is indeterminate. Do not set this bit. Reserved - The value read from this bit is indeterminate. Do not set this bit. ...

  • Page 79

    ... The value read from this bit is indeterminate. Do not set this bit. SPI interrupt Priority High bit SPIHSPILPriority Level 0 0 Lowest SPIH Highest Reserved - The value read from this bit is indeterminate. Do not set this bit. Keyboard interrupt Priority High bit KB DHKBDLPriority Level 0 0 Lowest KBDH Highest AT89C51RD2/ED2 SPIH - 0 KBDH 79 ...

  • Page 80

    ... Idle mode is detailed in Table 18-1. 18.2.1 Entering Idle Mode To enter Idle mode, set the IDL bit in PCON register (see Table 18-2). The AT89C51RD2/ED2 enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that sets IDL bit is the last instruction executed. ...

  • Page 81

    ... The status of the Port pins during Power-Down mode is detailed in Table 18-1. Note: 18.3.1 Entering Power-Down Mode To enter Power-Down mode, set PD bit in PCON register. The AT89C51RD2/ED2 enters the Power-Down mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is the last instruction executed. 18.3.2 ...

  • Page 82

    ... Reset initializes the AT89C51RD2/ED2 and vectors the CPU to address 0000h. 3. Generate an enabled external Keyboard interrupt (same behavior as external interrupt). Note: Note: Table 18-1. Mode Reset Idle (internal code) Idle (external ...

  • Page 83

    ... Cleared by hardware when an interrupt or reset occurs. PD Set to activate the Power-Down mode. If IDL and PD are both set, PD takes precedence. Idle Mode bit Cleared by hardware when an interrupt or reset occurs. IDL Set to activate the Idle mode. If IDL and PD are both set, PD takes precedence. AT89C51RD2/ED2 GF1 GF0 PD 0 IDL ...

  • Page 84

    ... Table 19-1. WDTRST - Watchdog Reset Register (0A6h Reset Value = XXXX XXXXb Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence. AT89C51RD2/ED2 make the best use of the WDT, it should be serviced in those sec- CLK PERIPH 7 counter has been added to extend the Time-out capability MHz ...

  • Page 85

    ... WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the AT89C51RD2/ED2 while in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode. ...

  • Page 86

    ... Pull ALE low while the device is in reset (RST high) and PSEN is high. • Hold ALE low as RST is deactivated. While the AT89C51RD2/ED2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit. Table 20-1 shows the status of the port pins during ONCE mode. ...

  • Page 87

    ... PD Cleared by hardware when reset occurs. Set to enter power-down mode. Idle mode bit IDL Cleared by hardware when interrupt or reset occurs. Set to enter idle mode. AT89C51RD2/ED2 switch-on. A warm start reset occurs while GF1 GF0 rises from 0 to its nominal voltage. Can also be set by ...

  • Page 88

    ... AUXR - Auxiliary Register (8Eh) 7 DPU Bit Number Reset Value = XX00 10’HSB. XRAM’0b Not bit addressable AT89C51RD2/ED2 88 AUXR Register XRS2 Bit Mnemonic Description Disable Weak Pull-up DPU Cleared by software to activate the permanent weak pull-up (default) Set by software to disable the weak pull-up (reduce power consumption) ...

  • Page 89

    ... EEBUSY flag in EECON is then set by hardware to indicate that programming is in progress and that the EEPROM segment is not available for reading or writing. • The end of programming is indicated by a hardware clear of the EEBUSY flag. Figure 23-1 represents the optimal write sequence to the on-chip EEPROM data memory. 4235K–8051–05/08 AT89C51RD2/ED2 89 ...

  • Page 90

    ... If the user application interrupts routines use XRAM memory space: Save and disable interrupts. • Load DPTR with the address to read • Set bit EEE of EECON register • Execute a MOVX A, @DPTR • Clear bit EEE of EECON register • Restore interrupts. AT89C51RD2/ED2 90 EEPROM Data Write Sequence EEBusy Cleared? Save & Disable IT ...

  • Page 91

    ... EECON = 02h (EEE=1) Data Read DPTR= Address ACC= Data Exec: MOVX A, @DPTR Last Byte to Read? EEPROM Data Mapping EECON = 00h (EEE = 0 Restore IT EECON Register Bit Mnemonic Description Reserved - The value read from this bit is indeterminate. Do not set this bit. AT89C51RD2/ED2 EEE EEBUSY 0 91 ...

  • Page 92

    ... Bit Number 1 0 Reset Value = XXXX XX00b Not bit addressable AT89C51RD2/ED2 92 Bit Mnemonic Description Enable EEPROM Space bit Set to map the EEPROM space during MOVX instructions (Write or Read to the EEE EEPROM. Clear to map the XRAM space during MOVX. Programming Busy flag Set by hardware when programming is in progress ...

  • Page 93

    ... EPROM programmer. The parallel programming method used by these devices is simi- lar to that used by EPROM 87C51 but it is not identical and the commercially available programmers need to have support for the AT89C51RD2/ED2. The bootloader and the Application Programming Interface (API) routines are located in the BOOT ROM. ...

  • Page 94

    ... Software registers are in a special page of the Flash memory which can be accessed through the API or with the parallel programming modes. This page, called "Extra Flash Memory", is not in the internal Flash program memory addressing space. 24.3.1 Hardware Register The only hardware register of the AT89C51RD2/ED2 is called Hardware Byte or Hardware Security Byte (HSB). Table 24- ...

  • Page 95

    ... Same as 2, also verify code memory through parallel programming interface disabled Same as 3, also external execution is disabled (Default). U: Unprogrammed or "one" level. P: Programmed or "zero" level not care WARNING: Security level 2 and 3 should only be programmed after Flash and code verification. Default Values Definition Software Boot Vector AT89C51RD2/ED2 Default value Description FCh 95 ...

  • Page 96

    ... Do not clear this bit. Reserved - Do not clear this bit. User Memory Lock Bits LB1-0 See Table 24-5 Default value Description 0FFh FFh 58h Atmel D7h C51 X2, Electrically Erasable ECh AT89C51RD2/ED2 64KB AT89C51RD2/ED2 64KB, EFh Revision LB1 4235K–8051–05/08 0 LB0 ...

  • Page 97

    ... Security Level Note: 24.4 Flash Memory Status AT89C51RD2/ED2 parts are delivered in standard with the ISP ROM bootloader. After ISP or parallel programming, the possible contents of the Flash memory are summarized in Figure 24-1: Figure 24-1. Flash Memory Possible Contents FFFFh Virgin 0000h Default After ISP 24 ...

  • Page 98

    ... Figure 24-2. Diagram Context Description Access Via Specific Protocol Access From User Application 24.6.2 Acronyms ISP: In-System Programming SBV: Software Boot Vector BSB: Boot Status Byte SSB: Software Security Byte HW: Hardware Byte AT89C51RD2/ED2 98 Bootloader Flash Memory 4235K–8051–05/08 ...

  • Page 99

    ... Flash Memory Management. • Flash Memory Management This process manages low level access to Flash memory (performs read and write access). 4235K–8051–05/08 ISP Communication Management Flash Memory Management Flash Memory AT89C51RD2/ED2 User Application User Call Management (API) 99 ...

  • Page 100

    ... To ensure correct microcontroller startup, the PSEN pin should not be tied to ground during power-on (See Figure 24-4. Hardware conditions typical sequence during power-on. The on-chip bootloader boot process is shown Table 24-6. Hardware Conditions BLJB SBV AT89C51RD2/ED2 100 Figure 24-4). VCC PSEN RST Bootloader Process Description ...

  • Page 101

    ... User Application 4235K–8051–05/08 RESET If BLJB = 0 then ENBOOT Bit (AUXR1) is Set else ENBOOT Bit (AUXR1) is Cleared Yes (PSEN = and ALE =1 or Not Connected) Hardware Condition? BLJB BLJB = 0 ENBOOT = 1 BSB = 00h ? SBV = FCh ? USER BOOT LOADER PC= [SBV]00h AT89C51RD2/ED2 Atmel BOOT LOADER 101 ...

  • Page 102

    ... Reclen field to and including the last byte of the Data/Info field. Therefore, the sum of all the ASCII pairs in a record after converting to binary, from the Reclen field to and including the Checksum field, is zero. AT89C51RD2/ED2 102 Record ...

  • Page 103

    ... Any access allowed Read-only access allowed Read-only access allowed Read-only access allowed Read-only access allowed Allowed Allowed Allowed AT89C51RD2/ED2 Level 1 Level 2 Any access not allowed Any access not allowed Any access not allowed Write level 2 allowed Read-only access allowed Read-only access allowed ...

  • Page 104

    ... This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency. The ISP feature requires that an initial character (an uppercase U) be sent to the AT89C51RD2/ED2 to establish the baud rate. Table show the autobaud capability. Table 24-8. ...

  • Page 105

    ... Sends Frame (made of 2 ASCII Characters Per Byte) Echo Analysis 4235K–8051–05/08 Autobaud Performances (Continued) 1.8432 2 2.4576 11.0592 ":" ":" AT89C51RD2/ED2 3.6864 14.746 Bootloader If (not received ":") Else Sends Echo and Start Reception Gets Frame, and Sends Back Echo for Each Received Byte 7 ...

  • Page 106

    ... Send Write Command OR Wait Checksum Error COMMAND ABORTED OR Wait Security Error COMMAND ABORTED Wait COMMAND_OK COMMAND FINISHED AT89C51RD2/ED2 106 Write Command ’X’ & CR & LF Send Checksum Error ’P’ & CR & LF Send Security Error ’.’ & CR & LF Bootloader Wait Write Command ...

  • Page 107

    ... 0000 0000 F5 0000 0000 Blank Check Command ’X’ & CR & LF ’.’ & CR & LF address & CR & LF AT89C51RD2/ED2 Bootloader Wait Blank Check Command Checksum Error Send Checksum Error Flash Blank Send COMMAND_OK Send First Address not Erased 107 ...

  • Page 108

    ... HOST BOOTLOADER Blank Check ok at address xxxx HOST BOOTLOADER Blank Check with checksum error HOST BOOTLOADER AT89C51RD2/ED2 108 : 05 0000 04 0000 7FFF 0000 04 0000 7FFF 0000 04 0000 7FFF 0000 04 0000 7FFF 01 78 xxxx 0000 04 0000 7FFF 0000 04 0000 7FFF 4235K–8051–05/08 ...

  • Page 109

    ... Value" CR & LF HOST : 05 0000 04 0000 0020 00 D7 BOOTLOADER : 05 0000 04 0000 0020 00 D7 0000=-----data------ CR LF (16 data) 0010=-----data------ CR LF (16 data) 0020=data CR LF AT89C51RD2/ED2 Bootloader Wait Display Command Checksum error Send Checksum Error RD_WR_SECURITY Send Security Error Read Data All Data Read ...

  • Page 110

    ... Example 24.9.9 ISP Commands Summary Table 24-9. ISP Commands Summary Command Command Name 00h Program Code AT89C51RD2/ED2 110 Read Command ’X’ & CR & LF ’L’ & CR & LF ’value’ & ’.’ & CR & LF Read function (read SBV) HOST : 02 0000 BOOTLOADER : 02 0000 Value ...

  • Page 111

    ... AT89C51RD2/ED2 Command Effect Erase block0 (0000h-1FFFh) Erase block1 (2000h-3FFFh) Erase block2 (4000h-7FFFh) Erase block3 (8000h- BFFFh) Erase block4 (C000h- FFFFh) Hardware Reset Erase SBV & BSB Program SSB level 1 Program SSB level 2 ...

  • Page 112

    ... To call the corresponding API, the user must use a set of Flash_api routines which can be linked with the application. Example of Flash_api routines are available on the Atmel web site on the software application note: C Flash Drivers for the AT89C51RD2/ED2 The API calls description and arguments are shown in 24.10.1 Process The application selects an API by setting R1, ACC, DPTR0 and DPTR1 registers. All calls are made through a common interface “ ...

  • Page 113

    ... DPL = 00h XXh ACC = ID1 DPL = 01h XXh ACC = ID2 XXXXh XXh ACC = Boot_Version AT89C51RD2/ED2 Command Effect Set SSB level 1 Set SSB level 2 Set SSB level 0 Set SSB level 1 Program boot status byte Program software boot vector Read Software Security Byte ...

  • Page 114

    ... V Output Low Voltage, port 0, ALE, PSEN OL1 V Output High Voltage, ports AT89C51RD2/ED2 114 Note: Stresses at or above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied ...

  • Page 115

    ... 1 (5) 50 200 75 7 2.25 2.5 2.15 2.35 70 140 ( RST = V (see Figure 25-2 must be externally limited as follows: OL AT89C51RD2/ED2 Max Unit Test Conditions 250 kΩ -50 V µA 0.45V < V ±10 µA -650 µ 150 2.7 < V µA 0.4 x Frequency (MHz ...

  • Page 116

    ... The maximum dV/dt value specifies the maximum Vcc drop to issure no internal POR/PFD reset. Figure 25-1. I Figure 25-2. I Figure 25-3. I AT89C51RD2/ED2 116 may exceed the related specification. Pins are not guaranteed to sink current greater OL Test Condition, Active Mode ...

  • Page 117

    ... CCIV 4235K–8051–05/08 V -0.5V CC 0.45V T CHCL CLCH = Time for Address Valid to ALE Low. AVLL = Time for ALE Low to PSEN Low. LLPL for -M and 20 MHz, Standard clock. LLIU AT89C51RD2/ED2 Tests in Active and Idle Modes CC 0.7V CC 0.2V -0 CLCH = 5ns. CHCL 117 ...

  • Page 118

    ... External Program Memory Characteristics Table 25-1. Table 25-2. AT89C51RD2/ED2 118 Symbol Description Symbol Parameter T Oscillator clock period T ALE pulse width LHLL T Address Valid to ALE AVLL T Address Hold After ALE LLAX T ALE to Valid Instruction In LLIV T ALE to PSEN LLPL T PSEN Pulse Width ...

  • Page 119

    ... Max PXIZ T Max AVIV T Max x PLAZ 12 T CLCL T T LHLL LLIV T LLPL T PLPH T LLAX T PLIV T T TPLAZ AVLL PXIX A0-A7 INSTR IN T AVIV ADDRESS A8-A15 AT89C51RD2/ED2 X parameter for X2 Clock -M range PXAV T PXIZ A0-A7 INSTR IN ADDRESS A8-A15 Units ns ns ...

  • Page 120

    ... Table 25-4. Table 25-5. AT89C51RD2/ED2 120 Symbol Description Symbol Parameter T RD Pulse Width RLRH T WR Pulse Width WLWH Valid Data In RLDV T Data Hold After RD RHDX T Data Float After RD RHDZ T ALE to Valid Data In LLDV T Address to Valid Data In AVDV T ALE LLWL T Address AVWL ...

  • Page 121

    ... LLWL T Max LLWL T Min AVWL T Min QVWX T Min QVWH T Min WHQX T Max x RLAZ T Min WHLH T Max WHLH T LLWL T QVWX T LLAX A0-A7 T AVWL ADDRESS A8-A15 OR SFR P2 AT89C51RD2/ED2 X parameter for X2 Clock -M range WHLH T WLWH T T WHQX QVWH DATA OUT ...

  • Page 122

    ... External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 25.3.7 Serial Port Timing - Shift Register Mode Table 25-7. Table 25-8. AT89C51RD2/ED2 122 T LLDV T LLWL T AVDV T LLAX A0-A7 T RLAZ T AVWL ADDRESS A8-A15 OR SFR P2 Symbol Description Symbol Parameter T Serial port clock cycle time ...

  • Page 123

    ... XLXL T XHQX XHDX T XHDV VALID VALID VALID VALID V -0.5V CC 0.7V CC 0.2V -0.1 0.45V CC T CHCL V -0.5V CC 0.45V CC min for a logic “1” and V IH AT89C51RD2/ED2 X Parameter For X2 Clock -M Range 133 SET TI VALID VALID VALID SET RI T CHCX T T CLCX CLCH T CLCL ...

  • Page 124

    ... For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded V ≥ ± 20 mA. 25.3.12 Clock Waveforms Valid in normal clock mode mode XTAL2 must be changed to XTAL2/2. AT89C51RD2/ED2 124 FLOAT V - 0.1V V ...

  • Page 125

    ... FLOAT INDICATES ADDRESS TRANSITIONS DPL OR Rt OUT FLOAT INDICATES DPH OR P2 SFR TO PCH TRANSITION DPL OR Rt OUT DATA OUT INDICATES DPH OR P2 SFR TO PCH TRANSITION OLD DATA NEW DATA P0 PINS SAMPLED P1, P2, P3 PINS SAMPLED RXD SAMPLED AT89C51RD2/ED2 STATE3 STATE4 STATE5 DATA ...

  • Page 126

    ... For PLCC68 and VQFP64 packages, please contact Atmel sales office for availability. AT89C51RD2/ED2 126 Temperature Supply Voltage Range Industrial & 2.7V - 5.5V Green Package Packing Product Marking PLCC44 Stick AT89C51RD2-UM VQFP44 Tray AT89C51RD2-UM VQFP64 Tray AT89C51RD2-UM PLCC68 Stick AT89C51RD2-UM PLCC44 Stick AT89C51ED2-UM VQFP44 Tray AT89C51ED2-UM PLCC68 Stick AT89C51ED2-UM VQFP64 ...

  • Page 127

    ... Packaging Information 27.1 PLCC44 4235K–8051–05/08 AT89C51RD2/ED2 127 ...

  • Page 128

    ... STANDARD NOTES FOR PLCC 1/ CONTROLLING DIMENSIONS : INCHES 2/ DIMENSIONING AND TOLERANCING PER ANSI Y 14.5M - 1982. 3/ "D" AND "E1" DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTUSIONS. MOLD FLASH OR PROTUSIONS SHALL NOT EXCEED 0.20 mm (.008 INCH) PER SIDE. AT89C51RD2/ED2 128 4235K–8051–05/08 ...

  • Page 129

    ... VQFP44 4235K–8051–05/08 AT89C51RD2/ED2 129 ...

  • Page 130

    ... DATUM "A" AND "D" DETERMINED AT DATUM PLANE H. 6/ DIMENSION " f " DOES NOT INCLUDE DAMBAR PROTUSION ALLOWABLE DAMBAR PROTUSION SHALL BE 0.08mm/.003" TOTAL IN EXCESS OF THE " f " DIMENSION AT MAXIMUM MATERIAL CONDITION . DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. AT89C51RD2/ED2 130 4235K–8051–05/08 ...

  • Page 131

    ... PLCC68 4235K–8051–05/08 AT89C51RD2/ED2 131 ...

  • Page 132

    ... VQFP64 AT89C51RD2/ED2 132 4235K–8051–05/08 ...

  • Page 133

    ... Removal of PDIL40 package offering. 28.9 Changes from 4235I - 04/07 to 4235J - 01/08 1. Minor corrections throughout the document. 2. Updated Package drawings. 28.10 Changes from 4235J - 01/08 to 4235K - 05/08 1. Removed non-green packages from product ordering information. 4235K–8051–05/08 min changed from 0 1 AT89C51RD2/ED2 + 0.9. CC 133 ...

  • Page 134

    ... Reset Input ......................................................................................................26 10.3 Reset Output ...................................................................................................26 11.1 Description .......................................................................................................28 12.1 Auto-reload Mode ............................................................................................30 12.2 Programmable Clock-output ............................................................................31 12.3 Registers .........................................................................................................32 13.1 PCA Capture Mode .........................................................................................43 13.2 16-bit Software Timer/ Compare Mode ...........................................................43 13.3 High Speed Output Mode ................................................................................44 13.4 Pulse Width Modulator Mode ..........................................................................45 13.5 PCA Watchdog Timer ......................................................................................46 AT89C51RD2/ED2 135 ...

  • Page 135

    ... Serial Port Interface (SPI) ...................................................................... 63 17 Interrupt System .................................................................................... 72 18 Power Management ............................................................................... 80 19 Hardware Watchdog Timer ................................................................... 84 20 ONCE 21 Power-off Flag ........................................................................................ 87 22 Reduced EMI Mode ................................................................................ 88 23 EEPROM Data Memory .......................................................................... 89 24 Flash/EEPROM Memory ........................................................................ 93 AT89C51RD2/ED2 136 14.1 Framing Error Detection ..................................................................................48 14.2 Automatic Address Recognition ......................................................................49 14.3 Registers .........................................................................................................51 14.4 Baud Rate Selection for UART for Mode 1 and 3 ...

  • Page 136

    ... Changes from 4235F - 09/04 to 4235G 08/05 ...............................................133 28.7 Changes from 4235G 08/05 to 4235H - 10/06 ..............................................133 28.8 Changes from 4235H - 10/06 to 4235I - 04/07 ..............................................133 28.9 Changes from 4235I - 04/07 to 4235J - 01/08 ...............................................133 28.10 Changes from 4235J - 01/08 to 4235K - 05/08 .............................................133 AT89C51RD2/ED2 137 ...

  • Page 137

    ... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...