TS87C54X2-VCB Atmel, TS87C54X2-VCB Datasheet - Page 29

• Manufacturer Part Number: TS87C54X2-VCB
• Description: IC MCU 8BIT 16K OTP 40MHZ 44PLCC
• Manufacturer: Atmel
• Series: 87Cr

Specifications of TS87C54X2-VCB

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40/30MHz
• Connectivity: UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

11. Idle mode
11.1
4431E–8051–04/06
Power-Down Mode
An instruction that sets PCON.0 causes that to be the last instruction executed before going into
the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but not to the
interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirely : the Stack
Pointer, Program Counter, Program Status Word, Accumulator and all other registers maintain
their data during Idle. The port pins hold the logical states they had at the time Idle was acti-
vated. ALE and PSEN hold at logic high levels.
There are two ways to terminate the Idle. Activation of any enabled interrupt will cause PCON.0
to be cleared by hardware, terminating the Idle mode. The interrupt will be serviced, and follow-
ing RETI the next instruction to be executed will be the one following the instruction that put the
device into idle.
The flag bits GF0 and GF1 can be used to give an indication if an interrupt occured during nor-
mal operation or during an Idle. For example, an instruction that activates Idle can also set one
or both flag bits. When Idle is terminated by an interrupt, the interrupt service routine can exam-
ine the flag bits.
The other way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is
still running, the hardware reset needs to be held active for only two machine cycles (24 oscilla-
tor periods) to complete the reset.
To save maximum power, a power-down mode can be invoked by software (Refer to Table 9-4.,
PCON register).
In power-down mode, the oscillator is stopped and the instruction that invoked power-down
mode is the last instruction executed. The internal RAM and SFRs retain their value until the
power-down mode is terminated. V
reset or an external interrupt can cause an exit from power-down. To properly terminate power-
down, the reset or external interrupt should not be executed before V
operating level and must be held active long enough for the oscillator to restart and stabilize.
Only external interrupts INT0 and INT1 are useful to exit from power-down. For that, interrupt
must be enabled and configured as level or edge sensitive interrupt input.
Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed
in Figure 11-1. When both interrupts are enabled, the oscillator restarts as soon as one of the
two inputs is held low and power down exit will be completed when the first input will be
released. In this case the higher priority interrupt service routine is executed.
Once the interrupt is serviced, the next instruction to be executed after RETI will be the one fol-
lowing the instruction that put TS80C54/58X2 into power-down mode.
CC
can be lowered to save further power. Either a hardware
AT/TS8xC54/8X2
CC
is restored to its normal
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