TS87C54X2-VCB Atmel, TS87C54X2-VCB Datasheet - Page 32

• Manufacturer Part Number: TS87C54X2-VCB
• Description: IC MCU 8BIT 16K OTP 40MHZ 44PLCC
• Manufacturer: Atmel
• Series: 87Cr

Specifications of TS87C54X2-VCB

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40/30MHz
• Connectivity: UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

12.1.1
32
AT/TS8xC54/8X2
WDT during Power Down and Idle
Table 12-2.
Reset value XXXX X000
In Power Down mode the oscillator stops, which means the WDT also stops. While in Power
Down mode the user does not need to service the WDT. There are 2 methods of exiting Power
Down mode: by a hardware reset or via a level activated external interrupt which is enabled prior
to entering Power Down mode. When Power Down is exited with hardware reset, servicing the
WDT should occur as it normally should whenever the TS80C54/58X2 is reset. Exiting Power
Down with an interrupt is significantly different. The interrupt is held low long enough for the
oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the
WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the
interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service routine.
To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is best
to reset the WDT just before entering powerdown.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the
TS80C54/58X2 while in Idle mode, the user should always set up a timer that will periodically
exit Idle, service the WDT, and re-enter Idle mode.
Number
Bit
7
6
5
4
3
2
1
0
T4
7
Mnemonic
Bit
WDTPRG Register
WDTPRG Address (0A7h)
T4
T3
T2
T1
T0
S2
S1
S0
T3
6
Reserved
Do not try to set or clear this bit.
WDT Time-out select bit 2
WDT Time-out select bit 1
WDT Time-out select bit 0
S2S1
0
0
0
0
1
1
1
1
T2
5
S0
0
0
1
1
0
0
1
1
Selected Time-out
0
1
0
1
0
1
0
1
T1
4
(2
(2
(2
(2
(2
(2
(2
(2
14
15
16
17
18
19
20
21
- 1) machine cycles, 16.3 ms @ 12 MHz
- 1) machine cycles, 32.7 ms @ 12 MHz
- 1) machine cycles, 65.5 ms @ 12 MHz
- 1) machine cycles, 131 ms @ 12 MHz
- 1) machine cycles, 262 ms @ 12 MHz
- 1) machine cycles, 542 ms @ 12 MHz
- 1) machine cycles, 1.05 s @ 12 MHz
- 1) machine cycles, 2.09 s @ 12 MHz
T0
3
Description
S2
2
S1
1
4431E–8051–04/06
S0
0