DSPIC30F4013T-20I/PT Microchip Technology, DSPIC30F4013T-20I/PT Datasheet
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... Microchip Technology Inc. High-Performance Digital Signal Controllers Advance Information Data Sheet DS70138C ...
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... PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... All DSP instructins are single cycle - Multiply-Accumulate (MAC) operation • Single cycle ±16 shift 2004 Microchip Technology Inc. dsPIC30F3014/4013 Peripheral Features: • High current sink/source I/O pins: 25 mA/25 mA • five 16-bit timers/counters; optionally pair up 16-bit timers into 32-bit timer modules • ...
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... V DD RF0 12 29 Vss RF1 13 28 OSC1/CLKIN U2RX/CN17/RF4 14 27 OSC2/CLKO/RC15 U2TX/CN18/RF5 15 26 U1RX/SDI1/SDA/RF2 16 25 EMUD3/U1TX/SDO1/SCL/RF3 17 24 INT0/RA11 EMUC3/SCK1/RF6 18 23 IC2/INT2/RD9 IC1/INT1/RD8 19 22 RD3 RD2 20 21 Vss V DD Advance Information Codec A/D 12-bit Interface 100 Ksps - AC’97 2004 Microchip Technology Inc ...
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... Pin Diagrams (Continued) 44-Pin TQFP U1RX/SDI1/SDA/RF2 U2TX/CN18/RF5 U2RX/CN17/RF4 RF1 RF0 EMUD2/OC2/RD1 EMUC2/OC1/RD0 AN12/RB12 AN11/RB11 Note: For descriptions of individual pins, see Section 1.0. 2004 Microchip Technology Inc. dsPIC30F3014/4013 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 32 2 OSC2/CLKO/RC15 31 3 OSC1/CLKIN dsPIC30F3014 28 6 AN8/RB8 27 7 PGD/EMUD/AN7/RB7 26 8 PGC/EMUC/AN6/OCFA/RB6 9 25 ...
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... Pin Diagrams (Continued) 44-Pin QFN U1RX/SDI1/SDA/RF2 1 U2TX/CN18/RF5 2 U2RX/CN17/RF4 3 RF1 4 RF0 EMUD2/OC2/RD1 9 EMUC2/OC1/RD0 10 AN12/RB12 11 Note: For descriptions of individual pins, see Section 1.0. DS70138C-page 4 OSC2/CLKO/RC15 33 OSC1/CLKIN dsPIC30F3014 28 AN8/RB8 27 PGD/EMUD/AN7/RB7 26 PGC/EMUC/AN6/OCFA/RB6 25 AN5/CN7/RB5 24 AN4/CN6/RB4 23 Advance Information 2004 Microchip Technology Inc. ...
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... AN2/SS1/LVDIN/CN4/RB2 PGC/EMUC/AN6/OCFA/RB6 PGD/EMUD/AN7/RB7 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 44-Pin TQFP U1RX/SDI1/SDA/RF2 U2TX/CN18/RF5 U2RX/CN17/RF4 CTX1/RF1 CRX1/RF0 EMUD2/OC2/RD1 EMUC2/OC1/RD0 AN12/COFS/RB12 AN11/CSDO/RB11 Note: For descriptions of individual pins, see Section 1.0. 2004 Microchip Technology Inc. dsPIC30F3014/4013 MCLR REF +/CN2/RB0 REF -/CN3/RB1 3 38 AN9/CSCK/RB9 4 37 AN10/CSDI/RB10 AN3/CN5/RB3 5 36 ...
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... Pin Diagrams (Continued) 44-Pin QFN U1RX/SDI1/SDA/RF2 U2TX/CN18/RF5 U2RX/CN17/RF4 CTX1/RF1 CRX1/RF0 EMUD2/OC2/RD1 EMUC2/OC1/RD0 10 AN12/COFS/RB12 11 For descriptions of individual pins, see Section 1.0. DS70138C-page OSC2/CLKO/RC15 2 32 OSC1/CLKIN dsPIC30F4013 AN8/RB8 PGD/EMUD/AN7/RB7 8 26 PGC/EMUC/AN6/OCFA/RB6 9 25 AN5/IC8/CN7/RB5 24 AN4/IC7/CN6/RB4 23 Advance Information 2004 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2004 Microchip Technology Inc. dsPIC30F3014/4013 Advance Information DS70138C-page 7 ...
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... NOTES: DS70138C-page 8 Advance Information 2004 Microchip Technology Inc. ...
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... 12-bit ADC Timers 2004 Microchip Technology Inc. dsPIC30F3014/4013 This document contains specific information for the dsPIC30F3014/4013 Digital Signal Controller (DSC) devices. The dsPIC30F3014/4013 devices contain extensive Digital Signal Processor (DSP) functionality within a high-performance 16-bit microcontroller (MCU) architecture. Figure 1-1 and Figure 1-2 show device block diagrams for dsPIC30F3014 and dsPIC30F4013 respectively ...
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... PORTA AN0/CN2/RB0 AN1/CN3/RB1 AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 AN4/IC7/CN6/RB4 AN5/IC8/CN7/RB5 PGC/EMUC/AN6/OCFA/RB6 PGD/EMUD/AN7/RB7 AN8/RB8 AN9/CSCK/RB9 AN10/CSDI/RB10 AN11/CSDO/RB11 AN12/COFS/RB12 PORTB EMUD1/SOSCI/T2CK/U1ATX/ CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/ CN0/RC14 OSC2/CLKO/RC15 PORTC EMUC2/OC1/RD0 EMUD2/OC2/RD1 OC3/RD2 OC4/RD3 IC1/INT1/RD8 IC2/INT2/RD9 PORTD C1RX/RF0 C1TX/RF1 U1RX/SDI1/SDA/RF2 EMUD3/U1TX/SDO1/SCL/RF3 U2RX/CN17/RF4 U2TX/CN18/RF5 EMUC3/SCK1/RF6 PORTF 2004 Microchip Technology Inc. ...
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... I/O PGC I Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input 2004 Microchip Technology Inc. dsPIC30F3014/4013 Buffer Type Analog Analog input channels. AN6 and AN7 are also used for device programming data and clock inputs, respectively. ...
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... Positive supply for logic and I/O pins. — Ground reference for logic and I/O pins. Analog Analog Voltage Reference (High) input. Analog Analog Voltage Reference (Low) input. Analog = Analog input O = Output P = Power Advance Information Description 2004 Microchip Technology Inc. ...
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... Section 3.2). The X and Y data space boundary is device specific and cannot be altered by the user. Each data word consists of 2 bytes, and most instructions can address data either as words or bytes. 2004 Microchip Technology Inc. dsPIC30F3014/4013 There are two methods of accessing data stored in program memory: • ...
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... The upper byte of the STATUS register contains the DSP Adder/Subtracter status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) status bit. 2.2.3 PROGRAM COUNTER The program counter is 23-bits wide; bit 0 is always clear. Therefore, the PC can address instruction words. Advance Information 2004 Microchip Technology Inc. ...
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... DSP AccA Accumulators AccB PC22 0 7 TABPAG TBLPAG Data Table Page Address 7 0 PSVPAG PSVPAG OAB SAB DA SRH 2004 Microchip Technology Inc. dsPIC30F3014/4013 D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD31 AD15 PC0 ...
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... The REPEAT loop count must be setup for 18 iterations of the DIV/ DIVF instruction. Thus, a complete divide operation requires 19 cycles. Note: The divide flow is interruptible. However, the user needs to save the context as appropriate. Function Advance Information 2004 Microchip Technology Inc. ...
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... ED EDAC MAC MAC MOVSAC MPY MPY.N MSC 2004 Microchip Technology Inc. dsPIC30F3014/4013 The DSP engine has various options selected through various bits in the CPU Core Configuration register (CORCON), as listed below: 1. Fractional or integer DSP multiply (IF). 2. Signed or unsigned DSP multiply (US). ...
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... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70138C-page 18 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Advance Information Round u Logic Zero Backfill 2004 Microchip Technology Inc. ...
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... B) as its pre- accumulation source and post-accumulation destina- tion. For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled via the barrel shifter, prior to accumulation. 2004 Microchip Technology Inc. dsPIC30F3014/4013 2.4.2.1 Adder/Subtracter, Overflow and Saturation ...
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... MAC class of instructions, the accumulator write back operation will function in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. Advance Information 2004 Microchip Technology Inc. ...
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... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. 2004 Microchip Technology Inc. dsPIC30F3014/4013 2.4.3 BARREL SHIFTER The barrel shifter is capable of performing up to 16-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...
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... NOTES: DS70138C-page 22 Advance Information 2004 Microchip Technology Inc. ...
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... UNITID (32 instr.) Reserved Device Configuration Registers Reserved DEVID (2) 2004 Microchip Technology Inc. dsPIC30F3014/4013 User program space access is restricted to the lower 4M instruction word address range (0x000000 to 0x7FFFFE) for all accesses other than TBLRD/TBLWT, which use TBLPAG<7> to determine user or configura- tion space access. In Table 3-1, Program Space Address Construction, bit 23 allows access to the Device ID, the User ID and the configuration bits ...
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... Program Space Address <23> <22:16> 0 TBLPAG<7:0> TBLPAG<7:0> PSVPAG<7:0> bits Program Counter Select 1 EA PSVPAG Reg 8 bits 15 bits EA TBLPAG Reg 8 bits 16 bits 24-bit EA Advance Information <15> <14:1> <0> PC<22:1> 0 Data EA<15:0> Data EA<15:0> Data EA<14:0> 0 Byte Select 2004 Microchip Technology Inc. ...
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... Program Memory ‘Phantom’ Byte (read as ‘0’) 2004 Microchip Technology Inc. dsPIC30F3014/4013 A set of table instructions are provided to move byte or word sized data to and from program space. 1. TBLRDL: Table Read Low Word: Read the LS Word of the program address; ...
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... Execution prior to exiting the loop due to an interrupt - Execution upon re-entering the loop after an interrupt is serviced • Any other iteration of the REPEAT loop will allow the instruction accessing data, using PSV, to execute in a single cycle. Advance Information 8 0 2004 Microchip Technology Inc. ...
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... PSVPAG is an 8-bit register, containing bits <22:15> of the program space address (i.e., it defines the page in program space to which the upper half of data space is being mapped). The memory map shown here is for a dsPIC30F4013 device. 2004 Microchip Technology Inc. dsPIC30F3014/4013 Program Space ...
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... EAs sourced from W10 and W11. The remaining X data space is addressed using W8 and W9. Both address spaces are concurrently accessed only with the MAC class instructions. The data space memory map is shown in Figure 3-7. Advance Information 2004 Microchip Technology Inc. ...
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... SFR Space 0x07FF 0x0801 0x0BFF 2 Kbyte 0x0C01 SRAM Space 0x0FFF 0x1001 0x1FFF 0x8001 Optionally Mapped into Program Memory 0xFFFF 2004 Microchip Technology Inc. dsPIC30F3014/4013 16 bits MSB LSB 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x0BFE 0x0C00 Y Data RAM (Y) 0x0FFE 0x1000 0x1FFE ...
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... DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W DS70138C-page 30 UNUSED Y SPACE UNUSED MAC Class Ops (Read) Indirect EA using W8, W9 Advance Information SFR SPACE UNUSED Indirect EA using W10, W11 2004 Microchip Technology Inc. ...
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... MAC instruction All effective addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes or 32K words. 2004 Microchip Technology Inc. dsPIC30F3014/4013 3.2.3 DATA SPACE WIDTH The core data width is 16 bits. All internal registers are organized as 16-bit wide words ...
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... A write to the SPLIM register should not be immediately followed by an indirect read operation using W15. FIGURE 3-10: 0x0000 15 PC<15:0> 000000000 <Free Word> Advance Information CALL STACK FRAME 0 W15 (before CALL) PC<22:16> W15 (after CALL) POP : [--W15] PUSH : [W15++] 2004 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F3014/4013 Advance Information DS70138C-page 33 ...
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... DS70138C-page 34 Advance Information 2004 Microchip Technology Inc. ...
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... Register Indirect Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset 2004 Microchip Technology Inc. dsPIC30F3014/4013 4.1.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space) ...
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... The only exception to the usage restrictions is for buff- ers which have a power-of-2 length. As these buffers satisfy the start and end address criteria, they may operate in a Bidirectional mode (i.e., address boundary checks will be performed on both the lower and upper address boundaries). Advance Information 2004 Microchip Technology Inc. ...
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... MODULO ADDRESSING OPERATION EXAMPLE Byte Address 0x0800 0x0863 Start Addr = 0x0800 End Addr = 0x0863 Length = 0x0032 words 2004 Microchip Technology Inc. dsPIC30F3014/4013 4.2.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control reg- registers: ister MODCON<15:0> contains enable flags as well register field to specify the W address registers ...
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... W register that has been designated as the bit-reversed pointer. Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer Advance Information N bytes, addressing and bit-reversed 2004 Microchip Technology Inc. ...
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... TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 1024 512 256 128 2004 Microchip Technology Inc. dsPIC30F3014/4013 Bit-Reversed Address Decimal XB<14:0> Bit-Reversed Address Modifier Value Advance Information A0 Decimal ...
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... NOTES: DS70138C-page 40 Advance Information 2004 Microchip Technology Inc. ...
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... Using NVMADR Addressing Using Table Instruction User/Configuration Space Select 2004 Microchip Technology Inc. dsPIC30F3014/4013 5.2 Run-Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes time and can write program memory data, 32 instructions (96 bytes time ...
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... NVMKEY register. Refer to Section 5.6 for DD further details. Note: The user can also directly write to the NVMADR and NVMADRU registers to specify a program memory address for erasing or programming. Advance Information 2004 Microchip Technology Inc. ...
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... MOV #0xAA,W1 MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP 2004 Microchip Technology Inc. dsPIC30F3014/4013 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Setup NVMCON register for multi-word, program Flash, program, and set WREN bit ...
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... Write PM high byte into program latch ; Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted Advance Information 2004 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F3014/4013 Advance Information DS70138C-page 45 ...
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... NOTES: DS70138C-page 46 Advance Information 2004 Microchip Technology Inc. ...
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... EEPROM write/erase operation. Attempting to read the data EEPROM while a programming or erase operation is in progress results in unspecified data. 2004 Microchip Technology Inc. dsPIC30F3014/4013 Control bit WR initiates write operations similar to pro- gram Flash writes. This bit cannot be cleared, only set, in software ...
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... Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence ; Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence Advance Information 2004 Microchip Technology Inc. ...
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... NOP ; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete 2004 Microchip Technology Inc. dsPIC30F3014/4013 The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...
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... EEPROM writes, various mechanisms have been built-in. On power-up, the WREN bit is cleared; also, the Power-up Timer prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch, or software malfunction. Advance Information 2004 Microchip Technology Inc. ...
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... WR TRIS WR LAT + WR Port Read LAT Read Port 2004 Microchip Technology Inc. dsPIC30F3014/4013 Any bit and its associated data and control registers that are not valid for a particular device will be dis- abled. That means the corresponding LATx and TRISx registers and the port pin will read as zeros. ...
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... EXAMPLE 7-1: MOV 0xFF00, W0 MOV W0, TRISB NOP btss PORTB, #11 Advance Information I/O Cell I/O Pad Input Data PORT WRITE/READ EXAMPLE ; Configure PORTB<15:8> inputs ; and PORTB<7:0> as outputs ; additional instruction cylcle ; bit test RB11 and skip if set 2004 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F3014/4013 Advance Information DS70138C-page 53 ...
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... Bit 1 Bit 0 Reset State CN1IE CN0IE 0000 0000 0000 0000 CN17IE CN16IE 0000 0000 0000 0000 CN1PUE CN0PUE 0000 0000 0000 0000 0000 0000 0000 0000 2004 Microchip Technology Inc. ...
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... The current CPU priority level is explicitly stored in the IPL bits. IPL<3> is present in the CORCON register, whereas IPL<2:0> are present in the STATUS register (SR) in the processor core. 2004 Microchip Technology Inc. dsPIC30F3014/4013 • INTCON1<15:0>, INTCON2<15:0> Global interrupt control functions are derived from these two registers ...
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... NVM - NVM Write Complete 2 SI2C - I C Slave Interrupt 2 MI2C - I C Master Interrupt Input Change Interrupt INT1 - External Interrupt 1 Reserved INT2 - External Interrupt 2 U2RX - UART2 Receiver U2TX - UART2 Transmitter Reserved C1 - Combined IRQ for CAN1 Reserved LVD - Low Voltage Detect Reserved 2004 Microchip Technology Inc. ...
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... LVD - Low Voltage Detect 43-53 51-61 Reserved Lowest Natural Order Priority 2004 Microchip Technology Inc. dsPIC30F3014/4013 8.2 Reset Sequence A Reset is not a true exception, because the interrupt controller is not involved in the Reset process. The pro- cessor initializes its registers in response to a Reset which forces the PC to zero ...
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... The arithmetic error trap (level 11) falls into this category of traps. ‘Hard’ traps include exceptions of priority level 12 through level 15, inclusive. The address error (level 12), stack error (level 13) and oscillator error (level 14) traps fall into this category. Advance Information 2004 Microchip Technology Inc. ...
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... STATUS register contains the processor priority level at the time prior to the beginning of the interrupt cycle. The processor then loads the priority level for this inter- 2004 Microchip Technology Inc. dsPIC30F3014/4013 rupt into the STATUS register. This action will disable all lower priority interrupts until the completion of the Interrupt Service Routine ...
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... At the same time, the processor will wake-up from Sleep or Idle and begin execution of the Interrupt Service Routine (ISR) needed to process the interrupt request. Advance Information 2004 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F3014/4013 Advance Information DS70138C-page 61 ...
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... DS70138C-page 62 Advance Information 2004 Microchip Technology Inc. ...
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... TGATE SOSCO/ T1CK LPOSCEN SOSCI 2004 Microchip Technology Inc. dsPIC30F3014/4013 These Operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1 presents a block diagram of the 16-bit timer module. 16-bit Timer Mode: In the 16-bit Timer mode, the timer ...
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... Low power • Real-Time Clock interrupts These operating modes are determined by setting the appropriate bit(s) in the T1CON Control register. FIGURE 9- pF 100K Advance Information RECOMMENDED COMPONENTS FOR TIMER1 LP OSCILLATOR RTC SOSCI 32.768 kHz dsPIC30FXXXX XTAL SOSCO R 2004 Microchip Technology Inc. ...
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... The TSIDL bit should be cleared to ‘0’ in order for RTC to continue operation in Idle mode. 2004 Microchip Technology Inc. dsPIC30F3014/4013 9.5.2 RTC INTERRUPTS When an interrupt event occurs, the respective interrupt flag, T1IF, is asserted and an interrupt will be generated if enabled ...
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... DS70138C-page 66 Advance Information 2004 Microchip Technology Inc. ...
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... Timer3 interrupt flag (T3IF) and the interrupt is enabled with the Timer3 interrupt enable bit (T3IE). 2004 Microchip Technology Inc. dsPIC30F3014/4013 16-bit Timer Mode: In the 16-bit mode, Timer2 and Timer3 can be configured as two independent 16-bit timers ...
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... Timer configuration bit T32 (T2CON<3>) must be set to ‘ bits are respective to the T2CON register. DS70138C-page TMR3 TMR2 MSB LSB Comparator x 32 PR3 PR2 Q D TGATE (T2CON<6> Gate Sync ’ for a 32-bit timer/counter operation. All control Advance Information Sync TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 2004 Microchip Technology Inc. ...
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... Reset 0 T3IF Event Flag 1 TGATE T3CK Note: T3CK pin does not exist on dsPIC30F3014/4013 devices. The block diagram shown here illustrates the schematic of Timer3 as implemented on the 30F6014 device. 2004 Microchip Technology Inc. dsPIC30F3014/4013 PR2 Comparator x 16 TMR2 Q D TGATE Q CK TON ...
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... In this mode, the T3IF interrupt flag is used as the source of the interrupt. The T3IF bit must be cleared in software. Enabling an interrupt is accomplished via the respective timer interrupt enable bit, T3IE (IEC0<7>). Advance Information 2004 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F3014/4013 Advance Information DS70138C-page 71 ...
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... NOTES: DS70138C-page 72 Advance Information 2004 Microchip Technology Inc. ...
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... T4CK Note: Timer configuration bit T32 (T4CON<3>) must be set to ‘ bits are respective to the T4CON register. 2004 Microchip Technology Inc. dsPIC30F3014/4013 The Operating modes of the Timer4/5 module are determined by setting the appropriate bit(s) in the 16-bit T4CON and T5CON SFRs. ...
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... TCS = 0, TGATE = 1 (gated time accumulation) DS70138C-page 74 PR4 Comparator x 16 TMR4 Q D TGATE Q CK TON 1 x Gate Sync PR5 Comparator x 16 TMR5 Q D TGATE Q CK Sync Advance Information Sync TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 2004 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F3014/4013 Advance Information DS70138C-page 75 ...
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... NOTES: DS70138C-page 76 Advance Information 2004 Microchip Technology Inc. ...
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... Data Bus Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture channels 1 through N. 2004 Microchip Technology Inc. dsPIC30F3014/4013 These Operating modes are determined by setting the appropriate bits in the ICxCON register (where x = 1,2,...,N). The dsPIC devices contain capture channels (i ...
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... IFSx Status register. Enabling an interrupt is accomplished via the respec- tive capture channel interrupt enable (ICxIE) bit. The capture interrupt enable bit is located in the corresponding IEC Control register. Advance Information module is defined as 2004 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F3014/4013 Advance Information DS70138C-page 79 ...
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... NOTES: DS70138C-page 80 Advance Information 2004 Microchip Technology Inc. ...
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... TMR3<15:0> Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1 through N. 2004 Microchip Technology Inc. dsPIC30F3014/4013 • Simple PWM mode • Output Compare During Sleep and Idle modes • Interrupt on Output Compare/PWM Event ...
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... FAULT condition has occurred. This state will be maintained until both of the following events have occurred: • The external FAULT condition has been removed. • The PWM mode has been re-enabled by writing to the appropriate control bits. Advance Information 2004 Microchip Technology Inc. ...
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... Timer3) is enabled and the TSIDL bit of the selected timer is set to logic ‘0’. 2004 Microchip Technology Inc. dsPIC30F3014/4013 When the selected TMRx is equal to its respective period register, PRx, the following four events occur on the next increment cycle: • ...
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... DS70138C-page 84 Advance Information 2004 Microchip Technology Inc. ...
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... Note: Both the transmit buffer (SPIxTXB) and the receive buffer (SPIxRXB) are mapped to the same register address, SPIxBUF. 2004 Microchip Technology Inc. dsPIC30F3014/4013 In Master mode, the clock is generated by prescaling the system clock. Data is transmitted as soon as a value is written to SPIxBUF. The interrupt is generated at the middle of the transfer of the last bit ...
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... Prescaler 1:1-1:8 Enable Master Clock SDOx SDIy SDIx SDOy LSb Serial Clock SCKx SCKy Advance Information Primary Prescaler F CY 1:1, 1:4, 1:16, 1:64 SPI™ Slave Serial Input Buffer (SPIyBUF) Shift Register (SPIySR) MSb LSb PROCESSOR 2 2004 Microchip Technology Inc. ...
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... The transmitter and receiver will stop in Sleep mode. However, register contents are not affected by entering or exiting Sleep mode. 2004 Microchip Technology Inc. dsPIC30F3014/4013 14.5 SPI Operation During CPU Idle Mode When the device enters Idle mode, all clock sources remain functional. The SPISIDL bit (SPIxSTAT< ...
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... DS70138C-page 88 Advance Information 2004 Microchip Technology Inc. ...
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... Thus, the I C module can operate either as a slave master bus. FIGURE 15-1: PROGRAMMER’S MODEL Bit 15 Bit 15 2004 Microchip Technology Inc. dsPIC30F3014/4013 15.1.1 VARIOUS I The following types • slave operation with 7-bit address 2 • slave operation with 10-bit address 2 • ...
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... Match Detect I2CADD Start and Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload Control I2CBRG BRG Down Counter CY F Advance Information Internal Data Bus Read Write Read Write Read Write Read Write Read Write Read 2004 Microchip Technology Inc. ...
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... SCL, such that SDA is valid during SCL high. The interrupt pulse is sent on the falling edge of the ninth clock pulse, regardless of the status of the ACK received from the master. 2004 Microchip Technology Inc. dsPIC30F3014/4013 15.3.2 SLAVE RECEPTION If the R_W bit received is a ‘ ...
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... SCLREL bit will not violate the minimum high time requirement for SCL. If the STREN bit is ‘0’, a software write to the SCLREL bit will be disregarded and have no effect on the SCLREL bit. Advance Information 2 CRCV 2004 Microchip Technology Inc. ...
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... When the interrupt is serviced, the source for the inter- rupt can be checked by reading the contents of the I2CRCV to determine if the address was device specific or a general call address. 2004 Microchip Technology Inc. dsPIC30F3014/4013 2 15. Master Support As a master device, six operations are supported: ...
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... C OPERATION DURING CPU IDLE MODE 2 For the I C, the I2CSIDL bit selects if the module will stop on Idle or continue on Idle. If I2CSIDL = 0, the module will continue operation on assertion of the Idle mode. If I2CSIDL = 1, the module will stop on Idle. Advance Information 2 C 2004 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F3014/4013 Advance Information DS70138C-page 95 ...
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... NOTES: DS70138C-page 96 Advance Information 2004 Microchip Technology Inc. ...
Page 99
... Data UxTX or UxATX if ALTIO=1 Parity Note 2004 Microchip Technology Inc. dsPIC30F3014/4013 • One or two Stop bits • Fully integrated baud rate generator with 16-bit prescaler • Baud rates range from 38 bps to 1.875 Mbps MHz instruction rate • 4-word deep transmit data buffer • ...
Page 100
... Load RSR to Buffer Receive Shift Register (UxRSR) 16 Divider 16x Baud Clock from Baud Rate Generator Advance Information Read Read Write UxMODE UxSTA – Generate Flags – Generate Interrupt – Shift Data Characters Control Signals UxRXIF 2004 Microchip Technology Inc. ...
Page 101
... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (power-on) setting of the UART is 8 bits, no parity and 1 Stop bit (typically represented 1). 2004 Microchip Technology Inc. dsPIC30F3014/4013 16.3 Transmitting Data 16.3.1 ...
Page 102
... UxRSR needs to transfer the character to the buffer. Once OERR is set, no further data is shifted in UxRSR (until the OERR bit is cleared in software or a Reset occurs). The data held in UxRSR and UxRXREG remains valid. Advance Information RXB) X 2004 Microchip Technology Inc. ...
Page 103
... FERR bit set. The break character is loaded into the buffer. No further reception can occur until a Stop bit is received. Note that RIDLE goes high when the Stop bit has not yet been received. 2004 Microchip Technology Inc. dsPIC30F3014/4013 16.6 Address Detect Mode Setting the ADDEN bit (UxSTA< ...
Page 104
... For the UART, the USIDL bit selects if the module will stop operation when the device enters Idle mode or whether the module will continue on Idle. If USIDL = 0, the module will continue operation during Idle mode. If USIDL = 1, the module will stop on Idle. Advance Information 2004 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F3014/4013 Advance Information DS70138C-page 103 ...
Page 106
... NOTES: DS70138C-page 104 Advance Information 2004 Microchip Technology Inc. ...
Page 107
... Programmable link to Input Capture module (IC2, for both CAN1 and CAN2) for time-stamping and network synchronization • Low power Sleep and Idle mode 2004 Microchip Technology Inc. dsPIC30F3014/4013 The CAN bus module consists of a protocol engine and message buffering/control. The CAN protocol engine handles all functions for receiving and transmitting messages on the CAN bus ...
Page 108
... Acceptance Filter c RXF3 c Acceptance Filter e RXF4 p t Acceptance Filter RXF5 R M Identifier Data Field Receive RERRCNT Error Counter TERRCNT Transmit Err Pas Error Bus Off Counter Protocol Finite State Machine Bit Timing Bit Timing Logic Generator (1) CiRX 2004 Microchip Technology Inc. ...
Page 109
... Module Disable mode. The I/O pins will revert to normal I/O function when the module is in the Module Disable mode. 2004 Microchip Technology Inc. dsPIC30F3014/4013 The module can be programmed to apply a low-pass filter function to the CiRX input line while the module or the CPU is in Sleep mode. The WAKFIL bit (CiCFG2< ...
Page 110
... End of Frame (EOF) field. Reading the RXnIF flag will indicate which receive buffer caused the interrupt. • Wake-up Interrupt: The CAN module has woken up from Disable mode or the device has woken up from Sleep mode. Advance Information 2004 Microchip Technology Inc. ...
Page 111
... SOF occurs. When TXREQ is set, the TXABT (CiTXnCON<6>), TXLARB (CiTXnCON<5>) and TXERR (CiTXnCON<4>) flag bits are automatically cleared. 2004 Microchip Technology Inc. dsPIC30F3014/4013 Setting TXREQ bit simply flags a message buffer as enqueued for transmission. When the module detects an available bus, it begins transmitting the message which has been determined to have the highest priority ...
Page 112
... definition, the nominal bit time has a minimum and a maximum the minimum nominal bit time is 1 µsec corresponding to a maximum bit rate of 1 MHz. Phase Segment 1 Segment 2 Sample Point Advance Information Q . Also, by definition, Phase Sync 2004 Microchip Technology Inc. ...
Page 113
... SEG1PH<2:0> (CiCFG2<5:3>), and Phase2 Seg is initialized by setting SEG2PH<2:0> (CiCFG2<10:8>). The following requirement must be fulfilled while setting the lengths of the phase segments: Prop Seg + Phase1 Seg > = Phase2 Seg 2004 Microchip Technology Inc. dsPIC30F3014/4013 17.6.5 SAMPLE POINT The sample point is the point of time at which the bus ...
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... DS70138C-page 112 Advance Information 2004 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F3014/4013 Advance Information DS70138C-page 113 ...
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... DS70138C-page 114 Advance Information 2004 Microchip Technology Inc. ...
Page 117
... CSDOM control bit. This allows other devices to place data on the serial bus during transmission periods not used by the DCI module. 2004 Microchip Technology Inc. dsPIC30F3014/4013 18.2.3 CSDI PIN The serial data input (CSDI) pin is configured as an input only pin when the module is enabled ...
Page 118
... DCI Mode Selection bits Receive Buffer Registers w/Shadow Transmit Buffer Registers w/Shadow DS70138C-page 116 BCG Control bits Sample Rate /4 Generator Frame Synchronization Generator DCI Buffer Control Unit 15 DCI Shift Register Advance Information SCKD CSCK FSD COFS 0 CSDI CSDO 2004 Microchip Technology Inc. ...
Page 119
... Note: The COFSG control bits will have no effect in AC-Link mode since the frame length is set to 256 CSCK periods by the protocol. 2004 Microchip Technology Inc. dsPIC30F3014/4013 18.3.4 FRAME SYNC MODE CONTROL BITS The type of frame sync signal is selected using the ...
Page 120
... LSB S12 S12 S12 Tag Tag Tag bit 2 bit 1 LSb MSb bit 14 bit 13 MSB LSB MSB 2 S protocol does not specify word length - this will Advance Information LSB 2004 Microchip Technology Inc. ...
Page 121
... DCI module. 2: When the CSCK signal is applied externally (CSCKD = 1), the external clock high and low times must meet the device timing requirements. 2004 Microchip Technology Inc. dsPIC30F3014/4013 EQUATION 18-2: The required bit clock frequency will be determined by the system sampling rate and frame size. Typical bit ...
Page 122
... In this case, the buffer control unit counter would be incre- mented twice during a data frame but only one receive register location would be filled with data. Advance Information 2004 Microchip Technology Inc. ...
Page 123
... DCI module. 2004 Microchip Technology Inc. dsPIC30F3014/4013 18.3.16 TRANSMIT STATUS BITS There are two transmit status bits in the DCISTAT SFR. The TMPTY bit is set when the contents of the transmit buffer registers are transferred to the transmit shadow registers ...
Page 124
... A/D and DAC data to 16 bits but permits proper data alignment in the TXBUF and RXBUF registers. Each RXBUF and TXBUF register will contain one data time slot value. Advance Information 2004 Microchip Technology Inc. ...
Page 125
... The user must also select the frame length and data word size using the COFSG and WS control bits in the DCICON2 SFR. 2004 Microchip Technology Inc. dsPIC30F3014/4013 2 18.7 FRAME AND DATA WORD ...
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... DS70138C-page 124 Advance Information 2004 Microchip Technology Inc. ...
Page 127
... Note: The ADCHS, ADPCFG and ADCSSL registers allow the application to configure AN13-AN15 as analog input pins. Since these pins are not physically present on the device, conversion results from these pins will read ‘ 2004 Microchip Technology Inc. dsPIC30F3014/4013 The A/D module has six 16-bit registers: • ...
Page 128
... Note: The ADCHS, ADPCFG and ADCSSL reg- isters allow the application to configure AN13-AN15 as analog input pins. Since these pins are not physically present on the device, conversion results from these pins will read ‘0’. Advance Information 2004 Microchip Technology Inc. ...
Page 129
... 5V). Refer to the Electrical Specifications section for minimum T operating conditions. Example 19-1 shows a sample calculation for the ADCS<5:0> bits, assuming a device operating speed of 30 MIPS. 2004 Microchip Technology Inc. dsPIC30F3014/4013 EXAMPLE 19-1: Minimum T ADCS<5:0> Therefore, Set ADCS<5:0> Actual T If SSRC< ...
Page 130
... The FORM<1:0> bits select the format. Each of the output formats translates to a 16-bit result on the data bus. Write data will always be in right justified (integer) format. Advance Information ≤ 3 kΩ HOLD C = DAC capacitance = negligible if Rs ≤ 2.5 kΩ. A/ 2004 Microchip Technology Inc. ...
Page 131
... Analog levels on any pin that is defined as a digital input (including the ANx pins) may cause the input buffer to consume current that exceeds the device specifications. 2004 Microchip Technology Inc. dsPIC30F3014/4013 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 ...
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... DS70138C-page 130 Advance Information 2004 Microchip Technology Inc. ...
Page 133
... In the Idle mode, the clock sources are still active but the CPU is shut-off. The RC oscillator option saves system cost while the LP crystal option saves power. 2004 Microchip Technology Inc. dsPIC30F3014/4013 20.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...
Page 134
... RC oscillator Note 1: dsPIC30F maximum operating frequency of 120 MHz must be met oscillator can be conveniently shared as system clock, as well as real-time clock for Timer1. 3: Requires external R and C. Frequency operation MHz. DS70138C-page 132 Description (1) (2) (3) OSC /4 output (3) Advance Information (1) (1) (1) 2004 Microchip Technology Inc. ...
Page 135
... FIGURE 20-1: OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 POR Done SOSCO 32 kHz LP Oscillator SOSCI 2004 Microchip Technology Inc. dsPIC30F3014/4013 PLL F PLL x4, x8, x16 PLL Lock Primary Osc Primary Oscillator Stability Detector Oscillator Start-up Timer Clock Switching Secondary Osc ...
Page 136
... FOS<2:0> FPR<4:0> Advance Information OSC cycles before releasing the OST OST . The T time is involved OSC2 Function OSC2 OSC2 OSC2 OSC2 OSC2 OSC2 OSC2 OSC2 OSC2 I OSC2 OSC2 CLKOUT CLKOUT I OSC2 (Notes (Notes (Notes 2004 Microchip Technology Inc. ...
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... Table 20-4. If OSCCON<14:12> are set to ‘111’ and FPR<4:0> are set to ‘00101’, ‘00110’ or ‘00111’, then a PLL multiplier (respectively) is applied. 2004 Microchip Technology Inc. dsPIC30F3014/4013 Note: When a 16x PLL is used, the FRC frequency must not be tuned to a frequency greater than 7 ...
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... Byte Write “0x78” to OSCCON high Byte Write “0x9A” to OSCCON high Byte write is allowed for one instruction cycle. Write the desired value or use bit manipulation instruction. Advance Information 2004 Microchip Technology Inc. ...
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... Set when PLL lock is achieved after a PLL start. Reset when lock is lost. Read zero when PLL is not selected as a system clock. bit 4 Unimplemented: Read as ‘0’ 2004 Microchip Technology Inc. dsPIC30F3014/4013 Note: The description of the OSCCON and OSCTUN SFRs, as well as the FOSC ...
Page 140
... Reset after FSCM switches the oscillator to (Group 1) FRC. Legend Readable bit -n = Value at POR y = Value set from configuration bits on POR DS70138C-page 138 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Advance Information x = Bit is unknown 2004 Microchip Technology Inc. ...
Page 141
... Center Frequency, Oscillator is running at calibrated frequency 1111 = 1110 = 1101 = 1100 = 1011 = 1010 = 1001 = 1000 =Minimum Frequency Legend Readable bit -n = Value at POR y = Value set from configuration bits on POR 2004 Microchip Technology Inc. dsPIC30F3014/4013 U-0 U-0 U-0 — — — U-0 U-0 R/W-0 — — ...
Page 142
... R = Readable bit DS70138C-page 140 — — — R/P — — — U R/P R/P — Writable bit U = Unimplemented bit, read as ‘0’ Advance Information U U — — bit 16 R/P R/P FOS<2:0> bit 8 R/P R/P R/P FPR<4:0> bit 0 2004 Microchip Technology Inc. ...
Page 143
... Reset state. The POR also selects the device clock source identified by the oscil- lator configuration fuses. 2004 Microchip Technology Inc. dsPIC30F3014/4013 Different registers are affected in different ways by var- ious Reset conditions. Most registers are not affected ...
Page 144
... PWRT TIME-OUT INTERNAL Reset FIGURE 20-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset DS70138C-page 142 OST T PWRT T T OST PWRT T OST T T PWRT Advance Information ) DD ): CASE CASE 2 DD 2004 Microchip Technology Inc. ...
Page 145
... Refer to the Electrical Specifications in the specific device data sheet for BOR voltage limit specifications. 2004 Microchip Technology Inc. dsPIC30F3014/4013 A BOR will generate a Reset pulse which will reset the device. The BOR will select the clock source based on the device configuration bit values (FOS< ...
Page 146
... When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. DS70138C-page 144 TRAPR IOPUWR EXTR SWR WDTO Idle Sleep POR BOR ( TRAPR IOPUWR EXTR SWR WDTO Idle Sleep POR BOR ( Advance Information 2004 Microchip Technology Inc. ...
Page 147
... In some devices, the LVD threshold voltage may be applied externally on the LVDIN pin. The LVD module is enabled by setting the LVDEN bit (RCON<12>). 2004 Microchip Technology Inc. dsPIC30F3014/4013 20.7 Power Saving Modes There are two power saving states that can be entered through the execution of a special instruction, PWRSAV ...
Page 148
... For additional infor- mation, please refer to the Programming Specifications of the device. Note: If the code protection configuration fuse bits (FGS<GCP> and FGS<GWRP>) have been programmed, an erase of the entire code-protected device is only possible at voltages V Advance Information ≥ 4.5V. DD 2004 Microchip Technology Inc. ...
Page 149
... In the dsPIC30F3014 device, the T4MD, T5MD, IC7MD, IC8MD, OC3MD, OC4MD and DCIMD are readable and writeable, and will be read as “1” when set. 2004 Microchip Technology Inc. dsPIC30F3014/4013 20.10 In-Circuit Debugger When MPLAB ICD2 is selected as a Debugger, the In- Circuit Debugging functionality is enabled. This func- tion allows simple debugging functions when used with MPLAB IDE ...
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... DS70138C-page 148 Advance Information 2004 Microchip Technology Inc. ...
Page 151
... The file register specified by the value ‘f’ • The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ 2004 Microchip Technology Inc. dsPIC30F3014/4013 Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: • ...
Page 152
... Moreover, double-word moves require instructions execute in two instruction cycles. Note: For more details on the instruction set, refer to the Programmer’s Reference Manual. Description Advance Information two cycles. The double-word 2004 Microchip Technology Inc. ...
Page 153
... Y data space pre-fetch address register for DSP instructions ∈ {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2, [W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2, [W11+W12], none} Y data space pre-fetch destination register for DSP instructions ∈ {W4..W7} Wyd 2004 Microchip Technology Inc. dsPIC30F3014/4013 Description Advance Information DS70138C-page 151 ...
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... None 1 1 (2) None 1 1 (2) None 1 1 (2) None 1 1 (2) None 1 1 (2) None 1 1 (2) None 1 1 (2) None 1 1 (2) None 1 1 (2) None 1 1 (2) None 1 2 None 1 1 (2) None 1 2 None 1 1 None 1 1 None 1 1 None 1 1 None 2004 Microchip Technology Inc. ...
Page 155
... DEC Ws,Wd 28 DEC2 DEC2 f DEC2 f,WREG DEC2 Ws,Wd 2004 Microchip Technology Inc. dsPIC30F3014/4013 Description Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws< ...
Page 156
... C,DC,N,OV C,DC,N, OA,OB,OAB, SA,SB,SAB 1 1 None 1 1 C,N,OV C,N,OV C,N, OA,OB,OAB, SA,SB,SAB 1 1 OA,OB,OAB, SA,SB,SAB 1 1 None None 1 1 None 1 1 None 1 1 None None 1 2 None 1 1 None 2004 Microchip Technology Inc. ...
Page 157
... RRC Ws,Wd 67 RRNC RRNC f RRNC f,WREG RRNC Ws,Wd 2004 Microchip Technology Inc. dsPIC30F3014/4013 Description Multiply Accumulator Square Wm to Accumulator -(Multiply Wm by Wn) to Accumulator Multiply and Subtract from Accumulator {Wnd+1, Wnd} = signed(Wb) * signed(Ws) {Wnd+1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd+1, Wnd} = unsigned(Wb) * signed(Ws) ...
Page 158
... C,DC,N,OV C,DC,N,OV C,DC,N,OV C,DC,N,OV C,DC,N,OV C,DC,N,OV C,DC,N,OV C,DC,N,OV C,DC,N,OV C,DC,N,OV C,DC,N,OV C,DC,N,OV C,DC,N,OV C,DC,N,OV C,DC,N,OV C,DC,N,OV C,DC,N,OV C,DC,N,OV None 1 1 None 1 2 None 1 2 None 1 2 None 1 2 None 1 1 None C,Z,N 2004 Microchip Technology Inc. ...
Page 159
... L - PICDEM MSC ® - microID - CAN ® - PowerSmart - Analog 2004 Microchip Technology Inc. dsPIC30F3014/4013 22.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. The MPLAB IDE is a Windows based application that contains: • ...
Page 160
... MPLAB C30 C Compiler and MPLAB ASM30 assembler. The simulator runs in either a Command Line mode for automated tasks, or from MPLAB IDE. This high-speed simulator is designed to debug, analyze and optimize time intensive DSP routines. Advance Information excellent, economical software 2004 Microchip Technology Inc. ...
Page 161
... The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 2004 Microchip Technology Inc. dsPIC30F3014/4013 22.11 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, ...
Page 162
... PICSTART Plus development pro- grammer, can be used to reprogram the device for user tailored application development. The PICDEM 17 demonstration board supports program download and execution from external on-board Flash memory. A generous prototype area is available for user hardware expansion. Advance Information 2004 Microchip Technology Inc. ...
Page 163
... PIC Microcontrollers” Handbook and a USB interface cable. Supports all current 8/14-pin Flash PIC microcontrollers, as well as many future planned devices. 2004 Microchip Technology Inc. dsPIC30F3014/4013 22.23 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB microcontrollers ...
Page 164
... NOTES: DS70138C-page 162 Advance Information 2004 Microchip Technology Inc. ...
Page 165
... V Range Temp Range 4.5-5.5V -40°C to 85°C 4.5-5.5V -40°C to 125°C 3.0-3.6V -40°C to 85°C 3.0-3.6V -40°C to 125°C 2.5-3.0V -40°C to 85°C 2004 Microchip Technology Inc. dsPIC30F3014/4013 DD (except V and MCLR) (Note 1) ..................................... -0. ....................................................................................................... 0V to +13.25V DD ) ..........................................................................................................± > ................................................................................................... ±20 mA Max MIPS dsPIC30FXXX-30I ...
Page 166
... W Typ Max Unit Notes 47 °C/W 1 39.3 °C/W 1 27.8 °C/W 1 -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Units Conditions V Industrial temperature V Extended temperature V V V/ms 0-5V in 0.1 sec 0- 2004 Microchip Technology Inc. ...
Page 167
... All I/O pins are configured as Inputs and pulled MCLR = V , WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data Memory are operational. No peripheral modules are operating. 2004 Microchip Technology Inc. dsPIC30F3014/4013 ) DD Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
Page 168
... DD measurements are as follows: OSC1 Advance Information 20 MIPS EC mode, 8X PLL 16 MIPS EC mode, 16X PLL 30 MIPS EC mode, 16X PLL FRC (~ 2 MIPS) LPRC (~ 512 kHz 2004 Microchip Technology Inc. ...
Page 169
... Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. IDLE 2: Base I current is measured with Core off, Clock on and all modules turned off. 2004 Microchip Technology Inc. dsPIC30F3014/4013 ) IDLE Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
Page 170
... Advance Information 20 MIPS EC mode, 8X PLL 16 MIPS EC mode, 16X PLL 30 MIPS EC mode, 16X PLL FRC (~ 2 MIPS) LPRC (~ 512 kHz) 2004 Microchip Technology Inc. ...
Page 171
... LVD, BOR, WDT, etc. are all switched off. The ∆ current is the additional current consumed when the module is enabled. This current should added to the base I current. 2004 Microchip Technology Inc. dsPIC30F3014/4013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial ...
Page 172
... T ≤ +125°C for Extended A Units Conditions µA -40°C µA 25°C 3.3V µA 85°C µA 125°C µA -40°C µA 25°C 5V µA 85°C µA 125°C Advance Information ) (CONTINUED) PD (3) Low Voltage Detect: ∆I LVD 2004 Microchip Technology Inc. ...
Page 173
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 5: Negative current is defined as current sourced by the pin. 2004 Microchip Technology Inc. dsPIC30F3014/4013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature ...
Page 174
... Advance Information ≤ +85°C for Industrial A ≤ +125°C for Extended A Units Conditions 8.5 mA 2.0 mA 1.6 mA 2.0 mA -3.0 mA -2.0 mA -1.3 mA -2.0 mA XTL, XT, HS and LP modes when external clock is used to drive OSC1 Osc mode mode 2004 Microchip Technology Inc. ...
Page 175
... These parameters are characterized but not tested in manufacturing. 2: These values not in usable operating range. FIGURE 23-2: BROWN-OUT RESET CHARACTERISTICS DD V BO10 (Device in Brown-out Reset) RESET (due to BOR) 2004 Microchip Technology Inc. dsPIC30F3014/4013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) Min (2) DD transition LVDL = 0000 — ...
Page 176
... Industrial A ≤ +125°C for Extended A Conditions -40°C ≤ T ≤ +85° Using EECON to read/write MIN V = Minimum operating voltage ms are violated Row Erase -40°C ≤ T ≤ +85°C A MIN Minimum operating voltage are violated ms Row Erase Bulk Erase 2004 Microchip Technology Inc. ...
Page 177
... LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 - for all pins except OSC2 Pin FIGURE 23-4: EXTERNAL CLOCK TIMING Q4 OSC1 CLKOUT 2004 Microchip Technology Inc. dsPIC30F3014/4013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ Operating voltage V range as described in DC Spec Section 23 ...
Page 178
... MHz EC with 16x PLL 4 MHz RC 4 MHz XTL MHz XT MHz XT with 4x PLL MHz XT with 8x PLL MHz XT with 16x PLL MHz HS kHz LP MHz FRC internal kHz LPRC internal — See parameter OS10 OSC for F value ns See Table 23- 2004 Microchip Technology Inc. ...
Page 179
... EC 0.200 Note 1: Assumption: Oscillator Postscaler is divide Instruction Execution Cycle Time Instruction Execution Frequency: MIPS = (F cycle]. 2004 Microchip Technology Inc. dsPIC30F3014/4013 = 2 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ Operating temperature -40°C ≤ (1) (2) Min Typ Max ...
Page 180
... V = 4.5-5 +25° 3.0-3 +25° 4.5-5.5 V ≤ ≤ +85° 3.0-3.6 V ≤ ≤ +85° 4.5-5.5 V ≤ ≤ +125° 4.5-5 +25° 3.0-3 +25° 4.5-5.5 V ≤ ≤ +85° 3.0-3.6 V ≤ ≤ +85° 4.5-5.5 V ≤ ≤ +125° 4.5-5.5 V 2004 Microchip Technology Inc. ...
Page 181
... Frequency calibrated at 25°C and 5V. TUN bits can be used to compensate for temperature drift. TABLE 23-19: INTERNAL RC ACCURACY AC CHARACTERISTICS Param Characteristic No. (1) LPRC @ Freq = 512 kHz F20 F21 Note 1: Frequency at 25°C and 5V. Change of LPRC frequency as V 2004 Microchip Technology Inc. dsPIC30F3014/4013 ≤ -40°C T ≤ -40°C T Min Typ Max Units ...
Page 182
... T A Operating temperature -40°C ≤ (1)(2)(3) (4) Min Typ — 10 — — — Advance Information ≤ +85°C for Industrial ≤ +125°C for Extended Max Units Conditions 25 ns — — — ns — — ns — OSC . 2004 Microchip Technology Inc. ...
Page 183
... SY12 MCLR Internal POR SY11 PWRT Time-out SY30 OSC Time-out Internal Reset Watchdog Timer Reset I/O Pins SY35 FSCM Delay Note: Refer to Figure 23-3 for load conditions. 2004 Microchip Technology Inc. dsPIC30F3014/4013 SY10 SY13 Advance Information SY20 SY13 DS70138C-page 181 ...
Page 184
... Band Gap Stable ≤ +85°C for Industrial A ≤ +125°C for Extended A Conditions Defined as the time between the instant that the band gap is enabled and the moment that the band gap reference voltage is stable. RCON<13>Status bit 2004 Microchip Technology Inc. ...
Page 185
... TCS (T1CON, bit 1)) CKEXTMRL TA20 T Delay from External TxCK Clock Edge to Timer Increment Note: Timer1 is a Type A. 2004 Microchip Technology Inc. dsPIC30F3014/4013 Tx11 Tx10 Tx15 OS60 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
Page 186
... OSC 6 T — ≤ +85°C for Industrial A ≤ +125°C for Extended A Max Units Conditions — ns Must also meet parameter TC15 — ns Must also meet parameter TC15 — prescale value (1, 8, 64, 256) OSC 6 T — 2004 Microchip Technology Inc. ...
Page 187
... Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2004 Microchip Technology Inc. dsPIC30F3014/4013 IC10 IC11 IC15 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
Page 188
... Operating temperature (1) (2) Min Typ Max Units — — TBD ns — — TBD ns Advance Information -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Conditions -40°C to +85° -40°C to +85° 2004 Microchip Technology Inc. ...
Page 189
... CSCK (SCKE = 1) COFS CS55 CS56 CS35 CS51 CS50 HIGH-Z CSDO CSDI Note: Refer to Figure 23-3 for load conditions. 2004 Microchip Technology Inc. dsPIC30F3014/4013 2 S MODES) TIMING CHARACTERISTICS CS11 CS10 CS21 CS20 MSb CS30 MSb IN CS40 CS41 Advance Information CS20 ...
Page 190
... Industrial A -40°C ≤ T ≤ +125°C for Extended A Units Conditions — ns — — ns — — ns — — ns — — — — — — — — ns — — ns — Note Note 1 — ns — — ns — 2004 Microchip Technology Inc. ...
Page 191
... These parameters are characterized but not tested in manufacturing. 2: These values assume BIT_CLK frequency is 12.288 MHz. 3: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2004 Microchip Technology Inc. dsPIC30F3014/4013 CS62 CS21 CS71 CS72 ...
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... Advance Information SP20 SP21 LSb LSb IN -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Max Units Conditions — ns — — ns — — — — — — — ns — — ns — 2004 Microchip Technology Inc. ...
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... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. 2004 Microchip Technology Inc. dsPIC30F3014/4013 SP10 SP21 SP35 SP20 BIT14 - - - - - -1 ...
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... T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Max Units Conditions — ns — — ns — — — — — — — ns — — ns — — ns — — — ns — 2004 Microchip Technology Inc. ...
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... SCK X (CKP = 0) SP71 X SCK (CKP = 1) MSb X SDO X SDI SDI MSb IN SP41 SP40 Note: Refer to Figure 23-3 for load conditions. 2004 Microchip Technology Inc. dsPIC30F3014/4013 SP70 SP73 SP35 SP72 SP52 BIT14 - - - - - -1 LSb SP30,SP31 BIT14 - - - -1 LSb IN Advance Information SP52 SP72 SP73 SP51 ...
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... T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Max Units Conditions — ns — — ns — — — — — — — ns — — ns — — ns — — — ns — — 2004 Microchip Technology Inc. ...
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... FIGURE 23-19 BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 SCL IM11 IM10 SDA In IM40 SDA Out Note: Refer to Figure 23-3 for load conditions. 2004 Microchip Technology Inc. dsPIC30F3014/4013 IM11 IM10 IM26 IM25 IM40 Advance Information IM34 IM33 Stop Condition IM21 ...
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... After this period the first clock pulse is µs generated µs µs — µs µs ns — — ns — ns — µs Time the bus must be free before a new µs transmission can start µ C)” 2004 Microchip Technology Inc. ...
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... SDA Start Condition 2 FIGURE 23-21 BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 SCL IS30 IS31 SDA In IS40 SDA Out 2004 Microchip Technology Inc. dsPIC30F3014/4013 IS11 IS10 IS26 IS25 IS40 Advance Information IS34 IS33 Stop Condition IS21 IS33 IS45 DS70138C-page 197 ...
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... Only relevant for repeated µs Start condition µs µs After this period the first µs clock pulse is generated µs µs — µs µs ns — — µs Time the bus must be free before a new transmission µs can start µs pF — 2004 Microchip Technology Inc. ...