AT80C51SND1C-ROTUL Atmel, AT80C51SND1C-ROTUL Datasheet
AT80C51SND1C-ROTUL
Specifications of AT80C51SND1C-ROTUL
Available stocks
Related parts for AT80C51SND1C-ROTUL
AT80C51SND1C-ROTUL Summary of contents
Page 1
... AT83SND1C: ROM • 4K Bytes of Boot Flash Memory (AT89C51SND1C) – ISP: Download from USB (standard) or UART (option) • External Code Memory – AT80C51SND1C: ROMless • USB Rev 1.1 Controller – Full Speed Data Transmission • Built-in PLL – MP3 Audio Clocks – ...
Page 2
... The AT89C51SND1C includes 64K Bytes of Flash memory and allows In-System Programming through an embedded 4K Bytes of Boot Flash memory. The AT83SND1C includes 64K Bytes of ROM memory. The AT80C51SND1C does not include any code memory. The AT8xC51SND1C include 2304 Bytes of RAM memory. The AT8xC51SND1C provides the necessary features for human interface like timers, keyboard port, serial or parallel interface (USB, TWI, SPI, IDE), ADC input, I memory interface (NAND or NOR Flash, SmartMedia, MultiMedia, DataFlash cards) ...
Page 3
Block Diagram Figure 3-1. AT8xC51SND1C Block Diagram INT0 INT1 VDD VSS 3 3 Interrupt Handler Unit RAM 2304 Bytes C51 (X2 Core) MP3 Decoder Clock and PLL Unit FILT X1 X2 RST ISP 1 Alternate function of Port 1 ...
Page 4
... VDD 11 AT80C51SND1C-RO (ROMLESS) PVDD 12 FILT 13 PVSS 14 VSS TST 18 UVDD 19 UVSS 20 1. ISP pin is only available in AT89C51SND1C product. Do not connect this pin on AT83SND1C product. 2. PSEN pin is only available in AT80C51SND1C product. 60 P4.5 59 P4.4 58 P2.2/A10 57 P2.3/A11 56 P2.4/A12 55 P2.5/A13 54 P2.6/A14 53 P2.7/A15 52 VSS 51 VDD MCLK 50 49 ...
Page 5
... MDAT DSEL SCLK DOUT P5.3 DCLK VSS AIN1 AVSS VDD P5.2 AREFP AREFN 1. ISP pin is only available in AT89C51SND1C product. Do not connect this pin on AT83SND1C and AT80C51SND1C product. 2. PSEN pin is only available in AT80C51SND1C product. AT8xC51SND1C P0.2/ P0.3/ VDD P5.0 AD2 AD3 1 ISP / P0 ...
Page 6
Figure 4-3. 4.2 Signals All the AT8xC51SND1C signals are detailed by functionality in Table 1 to Table 14. Table 1. Ports Signal Description AT8xC51SND1C 6 AT8xC51SND1C 84-pin PLCC Package ALE 12 ISP 13 P1.0/KIN0 14 P1.1/KIN1 15 P1.2/KIN2 16 P1.3/KIN3 ...
Page 7
Table 2. Clock Signal Description Table 3. Timer 0 and Timer 1 Signal Description 4109L–8051–02/08 Signal Name Type Description Port 3 P3.7:0 I 8-bit bidirectional I/O port with internal pull-ups. Port 4 P4.7:0 I ...
Page 8
Table 4. Audio Interface Signal Description Table 5. USB Controller Signal Description Table 6. MutiMediaCard Interface Signal Description AT8xC51SND1C 8 Signal Name Type Description Timer 0 External Clock Input T0 I When timer 0 operates as a counter, a falling ...
Page 9
Table 7. UART Signal Description Table 8. SPI Controller Signal Description Table 9. TWI Controller Signal Description Table 10. A/D Converter Signal Description 4109L–8051–02/08 Signal Name Type Description Receive Serial Data RXD I/O RXD sends and receives data in serial ...
Page 10
... ALE signals the start of an external bus cycle and indicates that valid ALE O address information is available on lines A7:0. An external latch is used to demultiplex the address from address/data bus. Program Store Enable Output (AT80C51SND1C Only) PSEN I/O This signal is active low during external code fetch or external code read (MOVC instruction). ...
Page 11
Table 14. Power Signal Description 4109L–8051–02/08 Signal Name Type Description Digital Supply Voltage VDD PWR Connect these pins to +3V supply voltage. Circuit Ground VSS GND Connect these pins to ground. Analog Supply Voltage AVDD PWR Connect this pin to ...
Page 12
Internal Pin Structure Table 15. Detailed Internal Pin Structure Notes: AT8xC51SND1C 12 Circuit VDD Watchdog Output 2 osc periods Latch Output 1. For information on resistors value, input/output levels, and drive capability, refer to the Section “DC Characteristics”, page ...
Page 13
Clock Controller The AT8xC51SND1C clock controller is based on an on-chip oscillator feeding an on-chip Phase Lock Loop (PLL). All internal clocks to the peripherals and CPU core are generated by this controller. 5.1 Oscillator The AT8xC51SND1C X1 and ...
Page 14
Note: Figure 5-3. Note: 5.3 PLL 5.3.1 PLL Description The AT8xC51SND1C PLL is used to generate internal high frequency clock (the PLL Clock) syn- chronized with an external low-frequency (the Oscillator Clock). The PLL clock provides ...
Page 15
Figure 5-4. Figure 5-5. 5.3.2 PLL Programming The PLL is programmed using the flow shown in Figure 5-6. As soon as clock generation is enabled, the user must wait until the lock indicator is set to ensure the clock output ...
Page 16
Registers Table 16. CKCON Register CKCON (S:8Fh) – Clock Control Register Reset Value = 0000 000Xb (AT89C51SND1C) or 0000 0000b (AT83SND1C) Table 17. PLLCON Register PLLCON (S:E9h) – PLL Control Register AT8xC51SND1C TWIX2 WDX2 - ...
Page 17
Reset Value = 0000 1000b Table 18. PLLNDIV Register PLLNDIV (S:EEh) – PLL N Divider Register Reset Value = 0000 0000b Table 19. PLLRDIV Register PLLRDIV (S:EFh) – PLL R Divider Register Reset Value = 0000 0000b 4109L–8051–02/08 Bit Bit ...
Page 18
... Program/Code Memory Organization FFFFh 64K Bytes External Code 0000h AT80C51SND1C 6.1 ROMLESS Memory Architecture As shown in Figure 6-2 the AT80C51SND1C external memory is composed of one space detailed in the following paragraph. AT8xC51SND1C 18 voltage, made possible by the internal charge pump. Thus, the DD FFFFh 64K Bytes ...
Page 19
... Multiplexed lower address lines and data for the external memory. Address Latch Enable ALE O ALE signals indicates that valid address information are available on lines AD7:0. Program Store Enable Output (AT80C51SND1C Only) PSEN O This signal is active low during external code fetch or external code read (MOVC instruction). AT8xC51SND1C ...
Page 20
... External Bus Cycles This section describes the bus cycles the AT80C51SND1C executes to fetch code (see Figure 6-4) in the external program/code memory. External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock peri- ods in standard mode or 6 oscillator clock periods in X2 mode. For further information on X2 mode see section “ ...
Page 21
Figure 6-6. 6.3.1 User Space This space is composed of a 64K Bytes Flash memory organized in 512 pages of 128 Bytes. It contains the user’s application code. This space can be read or written by both software and hardware ...
Page 22
Level 2 locks also hardware verifying of both user and boot memories Level 3 locks also the external execution. Table 21. Lock Bit Features Notes: 6.5 Boot Memory Execution As internal C51 code space is limited to 64K Bytes, some ...
Page 23
... AUXR1 (S:A2h) – Auxiliary Register 1 4109L–8051–02/08 RESET Hard Cond? ISP = L? Prog Cond? BLJB = P? Standard Init Prog Cond Init ENBOOT = 0 ENBOOT = 0000h PC = F000h FCON = F0h FCON = F0h User’s Atmel’s Application Boot Loader ENBOOT Bit Bit Number Mnemonic Description Reserved The value read from these bits are indeterminate ...
Page 24
Reset Value = XXXX 00X0b Note: 6.8 Hardware Bytes Table 23. HSB Byte – Hardware Security Byte Reset Value = XXUU UXXX, UUUU UUUU after an hardware full chip erase. Note: Table 24. SBV Byte – Software Boot Vector AT8xC51SND1C ...
Page 25
Reset Value = XXXX XXXX, UUUU UUUU after an hardware full chip erase. Table 25. SSB Byte – Software Security Byte Reset Value = XXXX XXXX, UUUU UUUU after an hardware full chip erase. 4109L–8051–02/08 Bit Bit Number Mnemonic Description ...
Page 26
Data Memory The AT8xC51SND1C provides data memory access in 2 different spaces: 1. The internal space mapped in three separate segments: – – – 2. The external space. A fourth internal segment is available but dedicated to Special Function ...
Page 27
The next 16 Bytes above the register banks form a block of bit-addressable memory space. The C51 instruction set includes a wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these instructions. ...
Page 28
Figure 3 shows the structure of the external address bus. P0 carries address A7:0 while P2 car- ries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 28 describes the external memory interface signals. Figure 3. External Data ...
Page 29
X2 mode. For further information on X2 mode, refer to the Section “X2 Feature”, page 13. Slow peripherals can be accessed by stretching the read and write cycles. This is done ...
Page 30
DPTR0 and DPTR1 are seen by the CPU as DPTR and are accessed using the SFR addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1 register (see Table 22) is used to select ...
Page 31
Registers Table 29. PSW Register PSW (S:8Eh) – Program Status Word Register Reset Value = 0000 0000b Table 30. AUXR Register AUXR (S:8Eh) – Auxiliary Control Register 4109L–8051–02/ Bit Bit Number Mnemonic Description ...
Page 32
Reset Value = X000 1101b AT8xC51SND1C 32 Bit Bit Number Mnemonic Description External RAM Enable Bit Set to select the external XRAM when executing MOVX @Ri or MOVX @DPTR 1 EXTRAM instructions. Clear to select the internal expanded RAM when ...
Page 33
Special Function Registers The Special Function Registers (SFRs) of the AT8xC51SND1C derivatives fall into the catego- ries detailed in Table 31 to Table 47. The relative addresses of these SFRs are provided together with their reset values in Table ...
Page 34
Table 34. Interrupt SFRs (Continued) Mnemonic Add Name IPL1 B2h Interrupt Priority Control Low 1 Table 35. Port SFRs Mnemonic Add Name P0 80h 8-bit Port 0 P1 90h 8-bit Port 1 P2 A0h 8-bit Port 2 P3 B0h 8-bit ...
Page 35
Table 38. MP3 Decoder SFRs (Continued) Mnemonic Add Name MP3DAT ACh MP3 Data MP3ANC ADh MP3 Ancillary Data MP3VOL 9Eh MP3 Audio Volume Control Left MP3 Audio Volume Control MP3VOR 9Fh Right MP3BAS B4h MP3 Audio Bass Control MP3MED B5h ...
Page 36
Table 40. USB Controller SFRs Mnemonic Add Name USBCON BCh USB Global Control USBADDR C6h USB Address USBINT BDh USB Global Interrupt USBIEN BEh USB Global Interrupt Enable UEPNUM C7h USB Endpoint Number UEPCONX D4h USB Endpoint X Control UEPSTAX ...
Page 37
Table 43. Serial I/O Port SFRs Mnemonic Add Name SCON 98h Serial Control SBUF 99h Serial Data Buffer SADEN B9h Slave Address Mask SADDR A9h Slave Address BDRCON 92h Baud Rate Control BRL 91h Baud Rate Reload Table 44. SPI ...
Page 38
Table 48. SFR Addresses and Reset Values 0/8 1/9 UEPINT DAT16H F8h 0000 0000 XXXX XXXX (1) B F0h 0000 0000 PLLCON E8h 0000 1000 (1) ACC E0h 0000 0000 (1) P5 D8h XXXX 1111 (1) (3) PSW FCON D0h ...
Page 39
Interrupt System The AT8xC51SND1C, like other control-oriented computer architectures, employ a program interrupt method. This operation branches to a subroutine and performs some service in response to the interrupt. When the subroutine completes, execution resumes at the point where ...
Page 40
Table 50. Priority Levels A low-priority interrupt is always interrupted by a higher priority interrupt but not by another inter- rupt of lower or equal priority. Higher priority interrupts are serviced before lower priority interrupts. The response to simultaneous occurrence ...
Page 41
Figure 9-1. Interrupt Control System External INT0 Interrupt 0 Timer 0 External INT1 Interrupt 1 Timer 1 TXD Serial Port RXD MP3 Decoder Audio Interface MCLK MMC MDAT Controller MCMD SCL TWI Controller SDA SCK SPI SI Controller SO A ...
Page 42
External Interrupts 9.2.1 INT1:0 Inputs External interrupts INT0 and INT1 (INTn pins may each be programmed to be level- triggered or edge-triggered, dependent upon bits IT0 and IT1 (ITn ...
Page 43
Registers Table 52. IEN0 Register IEN0 (S:A8h) – Interrupt Enable Register 0 Reset Value = 0000 0000b 9.3.0.1 Table 53. IEN1 Register IEN1 (S:B1h) – Interrupt Enable Register 1 4109L–8051–02/ EAUD EMP3 Bit Bit Number ...
Page 44
Reset Value = 0000 0000b 9.3.0.2 Table 54. IPH0 Register IPH0 (S:B7h) – Interrupt Priority High Register 0 AT8xC51SND1C 44 Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is always 0. Do not set ...
Page 45
Reset Value = X000 0000b Table 55. IPH1 Register IPH1 (S:B3h) – Interrupt Priority High Register 1 Reset Value = 0000 0000b 4109L–8051–02/08 Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do ...
Page 46
Table 56. IPL0 Register IPL0 (S:B8h) - Interrupt Priority Low Register 0 Reset Value = X000 0000b 9.3.0.3 Table 57. IPL1 Register IPL1 (S:B2h) – Interrupt Priority Low Register 1 AT8xC51SND1C IPLAUD IPLMP3 Bit Bit ...
Page 47
Reset Value = 0000 0000b 4109L–8051–02/08 Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is always 0. Do not set this bit. USB Interrupt Priority Level LSB 6 IPLUSB Refer to Table 50 for ...
Page 48
Power Management 2 power reduction modes are implemented in the AT8xC51SND1C: the Idle mode and the Power-down mode. These modes are detailed in the following sections. In addition to these power reduction modes, the clocks of the core and ...
Page 49
To determine the capacitor value to implement, the highest value of these 2 parameters has to be chosen. different oscillator startup and V Table 59. Minimum Reset Capacitor Value for a 50 kΩ Pull-down Resistor Oscillator Start-Up Time Note: 10.1.2 ...
Page 50
Idle Mode Idle mode is a power reduction mode that reduces the power consumption. In this mode, pro- gram execution halts. Idle mode freezes the clock to the CPU at known states while the peripherals continue to be clocked ...
Page 51
Entering Power-down Mode To enter Power-down mode, set PD bit in PCON register. The AT8xC51SND1C enters the Power-down mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is the last instruction executed. ...
Page 52
Notes: 10.5 Registers Table 60. PCON Register PCON (S:87h) – Power Configuration Register Reset Value = 00XX 0000b AT8xC51SND1C 52 A logic high on the RST pin clears PD bit in PCON register directly and asynchronously. This starts the ...
Page 53
Timers/Counters The AT8xC51SND1C implement 2 general-purpose, 16-bit Timers/Counters. They are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer event Counter. When operating ...
Page 54
Figure 11-1. Timer 0 and Timer 1 Clock Controller and Symbols PER CLOCK OSC ÷ 2 CLOCK CKCON.1 TIM0 CLOCK Timer 0 Clock Symbol 11.3 Timer 0 Timer 0 functions as either a Timer or event Counter in four modes ...
Page 55
Figure 11-3. Mode 0 Overflow Period Formula 11.3.2 Mode 1 (16-bit Timer) Mode 1 configures Timer 16-bit Timer with TH0 and TL0 registers connected in cascade (see Figure 11-4). The selected input increments TL0 register. Figure 11-5 ...
Page 56
Mode 3 (2 8-bit Timers) Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bit Timers (see Figure 11-8). This mode is provided for applications requiring an additional 8-bit Timer or Counter. TL0 uses ...
Page 57
When Timer mode 3, it uses Timer 1’s overflow flag (TF1) and run control bit (TR1). For this situation, use Timer 1 only for applications that do not require an interrupt (such as a Baud Rate ...
Page 58
Reset Value = 0000 0000b Table 62. TMOD Register TMOD (S:89h) – Timer/Counter Mode Control Register AT8xC51SND1C 58 Bit Bit Number Mnemonic Description Timer 1 Overflow Flag 7 TF1 Cleared by hardware when processor vectors to interrupt routine. Set by ...
Page 59
Notes: Reset Value = 0000 0000b Table 63. TH0 Register TH0 (S:8Ch) – Timer 0 High Byte Register Reset Value = 0000 0000b Table 64. TL0 Register TL0 (S:8Ah) – Timer 0 Low Byte Register 4109L–8051–02/08 Bit Bit Number Mnemonic ...
Page 60
Reset Value = 0000 0000b Table 65. TH1 Register TH1 (S:8Dh) – Timer 1 High Byte Register Reset Value = 0000 0000b Table 66. TL1 Register TL1 (S:8Bh) – Timer 1 Low Byte Register Reset Value = 0000 0000b AT8xC51SND1C ...
Page 61
Watchdog Timer The AT8xC51SND1C implement a hardware Watchdog Timer (WDT) that automatically resets the chip allowed to time out. The WDT provides a means of recovering from routines that do not complete successfully due to software ...
Page 62
Watchdog Operation After reset, the WDT is disabled. The WDT is enabled by writing the sequence 1Eh and E1h into the WDTRST register. As soon enabled, there is no way except the chip reset to disable ...
Page 63
Registers Table 68. WDTRST Register WDTRST (S:A6h Write only) – Watchdog Timer Reset Register Reset Value = XXXX XXXXb Figure 12-4. WDTPRG Register WDTPRG (S:A7h) – Watchdog Timer Program Register Reset Value = XXXX X000b 4109L–8051–02/ ...
Page 64
MP3 Decoder The AT8xC51SND1C implement a MPEG I/II audio layer 3 decoder better known as MP3 decoder. In MPEG I (ISO 11172-3) three layers of compression have been standardized supporting three sampling frequencies: 48, 44.1, and 32 kHz. Among ...
Page 65
Each time the MP3 decoder needs MP3 data, it sets the MPREQ, MPFREQ and MPBREQ flags respectively in MP3STA and MP3STA1 registers. MPREQ flag can generate an interrupt if enabled as ...
Page 66
Table 70. Volume Control 13.2.2 Equalization Control Sound can be adjusted using a 3-band equalizer: a bass band under 750 Hz, a medium band from 750 Hz to 3300 Hz and a treble band over 3300 Hz. The MP3BAS, MP3MED, ...
Page 67
Frame Information The MP3 frame header contains information on the audio data contained in the frame. These informations is made available in the MP3STA register for you information. MPVER and MPFS1:0 bits allow decoding of the sampling frequency according ...
Page 68
Figure 13-5. MP3 Decoder Interrupt System 13.6.2 Management Reading the MP3STA register automatically clears the interrupt flags (acknowledgment) except the MPREQ and MPANC flags. This implies that register content must be saved and tested, interrupt flag by interrupt flag to ...
Page 69
Figure 13-6. MP3 Interrupt Service Routine Flow Note: 13.7 Registers Table 73. MP3CON Register MP3CON (S:AAh) – MP3 Decoder Control Register 4109L–8051–02/08 Data Request Handler Write MP3 Data to MP3DAT Synchro Error Handler Reload MP3 Frame Through MP3DAT 1. Test ...
Page 70
Reset Value = 0011 1111b Table 74. MP3STA Register MP3STA (S:C8h Read Only) – MP3 Decoder Status Register AT8xC51SND1C 70 Bit Bit Number Mnemonic Description Bass Boost Bit 6 MPBBST Set to enable the bass boost sound effect. Clear to ...
Page 71
Reset Value = 0000 0001b Table 75. MP3DAT Register MP3DAT (S:ACh) – MP3 Data Register Reset Value = 0000 0000b Table 76. MP3STA1 Register MP3STA1 (S:AFh) – MP3 Decoder Status Register 1 Reset Value = 0001 0001b Table 77. MP3ANC ...
Page 72
Reset Value = 0000 0000b Table 78. MP3VOL Register MP3VOL (S:9Eh) – MP3 Volume Left Control Register Reset Value = 0000 0000b Table 79. MP3VOR Register MP3VOR (S:9Fh) – MP3 Volume Right Control Register Reset Value = 0000 0000b Table ...
Page 73
Table 81. MP3MED Register MP3MED (S:B5h) – MP3 Medium Control Register Reset Value = 0000 0000b Table 82. MP3TRE Register MP3TRE (S:B6h) – MP3 Treble Control Register Reset Value = 0000 0000b Table 83. MP3CLK Register MP3CLK (S:EBh) – MP3 ...
Page 74
Audio Output Interface The AT8xC51SND1C implement an audio output interface allowing the audio bitstream to be output in various formats compatible with right and left justification PCM and I and thanks to the on-chip PLL (see Section ...
Page 75
The audio interface clock frequency depends on the incoming MP3 frames and the audio DAC used. Figure 14-2. Audio Clock Generator and Symbol As soon as audio interface is enabled by setting AUDEN bit in AUDCON1 ...
Page 76
Figure 14-4. Audio Output Format DSEL DCLK 1 2 DOUT LSB MSB B14 DSEL DCLK 1 2 DOUT MSB B14 DSEL DCLK 1 2 DOUT MSB B14 DSEL DCLK 1 DOUT DSEL DCLK 1 DOUT MSB B16 The data converter ...
Page 77
Table 84. Sample Duplication Factor 14.5 MP3 Buffer In song playing mode, the audio stream comes from the MP3 decoder through a buffer. The MP3 buffer is used to store the decoded MP3 data and interfaces to the decoder through ...
Page 78
Figure 14-6. MP3 Mode Audio Configuration Flow 14.8 Voice or Sound Playing In voice or sound playing mode, the operations required are to configure the PLL and the audio interface according to the DAC selected. The audio clock is programmed ...
Page 79
Reset Value = 0000 1000b Table 86. AUDCON1 Register AUDCON1 (S:9Bh) – Audio Interface Control Register 1 Reset Value = 1011 0010b Table 87. AUDSTA Register AUDSTA (S:9Ch Read Only) – Audio Interface Status Register 4109L–8051–02/08 Bit Bit Number Mnemonic ...
Page 80
Reset Value = 1100 0000b Table 88. AUDDAT Register AUDDAT (S:9Dh) – Audio Interface Data Register Reset Value = 1111 1111b Table 89. AUDCLK Register AUDCLK (S:ECh) – Audio Clock Divider Register Reset Value = 0000 0000b AT8xC51SND1C 80 Bit ...
Page 81
Universal Serial Bus The AT8xC51SND1C implements a USB device controller supporting full speed data transfer. In addition to the default control endpoint 0, it provides 2 other endpoints, which can be configured in control, bulk, interrupt or isochronous modes: ...
Page 82
Figure 15-3 shows how to connect the AT8xC51SND1C to the USB connector. D+ and D- pins are connected through 2 termination resistors. A pull-up resistor is implemented inform the host of a full speed device connection. Value ...
Page 83
Bit stuffing and unstuffing. • CRC generation and checking. • ACKs and NACKs automatic generation. • TOKEN type identifying. • Address checking. • Clock recovery (using DPLL). Figure 15-4. SIE Block Diagram End of Packet Start of Packet D+ ...
Page 84
Figure 15-5. UFI Block Diagram 12 MHz DPLL Endpoint Control To/From SIE Figure 15-6. USB Typical Transaction Load OUT Transactions: HOST OUT DATA0 (n Bytes) UFI C51 IN Transactions: HOST IN UFI NACK Endpoint FIFO Write C51 15.2 Configuration 15.2.1 ...
Page 85
Set configuration The CONFG bit in the USBCON register should be set after a SET_CONFIGURATION request with a non-zero value. Otherwise, this bit should be cleared. 15.2.2 Endpoint Configuration • Selection of an Endpoint The endpoint register access is ...
Page 86
For Control endpoints, the EPDIR bit has no effect. • Summary of Endpoint Configuration: Do not forget to select the correct endpoint number in the UEPNUM register before access- ing endpoint specific registers. Table 90. Summary of Endpoint ...
Page 87
Warning 1: The Byte counter is not updated. Warning 2: Do not write more Bytes than supported by the corresponding endpoint. 15.3.3 FIFO Mapping Figure 15-8. Endpoint FIFO Configuration UEPSTA0 Endpoint 0 UEPSTA2 Endpoint 2 15.4 Bulk/Interrupt Transactions Bulk and ...
Page 88
ZLP (Zero Length Packet), the UBYCTX register value is equal to 0 and no data has to be read. When all the endpoint FIFO Bytes have been read, the firmware should clear the RXOUTB0 bit to allow the ...
Page 89
FIFO before clearing the RXOUTB1 bit. Until the RXOUTB1 bit has been cleared by the firmware, the USB controller will answer a NAK handshake for each OUT requests on the bank 1 endpoint FIFO. The RXOUTB0 and RXOUTB1 bits ...
Page 90
All USB retry mechanisms are automatically managed by the USB controller. 15.4.4 Bulk/Interrupt IN Transactions in Ping-pong Mode Figure 15-12. Bulk/Interrupt IN transactions in Ping-pong mode An endpoint should be first enabled and configured before being able to send Bulk ...
Page 91
The firmware should never write more Bytes than supported by the endpoint FIFO. 15.5 Control Transactions 15.5.1 Setup Stage The DIR bit in the UEPSTAX register should Receiving Setup packets is the same as receiving Bulk Out ...
Page 92
ZLP (Zero Length Packet), the UBYCTX register value is equal to 0 and no data has to be read. The STLCRC bit in the UEPSTAX register is set by the USB controller if the packet stored in FIFO has ...
Page 93
If the TXRDY bit is not set when the IN request occurs, nothing will be sent by the USB controller. When the IN packet has been sent, the TXCMPL bit in the UEPSTAX register is set by the USB controller. ...
Page 94
Important note: when a Clear Halt Feature occurs for an endpoint, the firmware should reset this endpoint using the UEPRST resgister in order to reset the data toggle management. 15.7.3 Start of Frame Detection The SOFINT bit in the USBINT ...
Page 95
The firmware has to clear the SPINT bit in the USBINT register before any other USB operation in order to wake up the USB controller from its Suspend mode. The USB controller is then re-activated. Figure 15-13. Example of a ...
Page 96
Figure 15-14. Example of REMOTE WAKEUP Management SET_FEATURE: DEVICE_REMOTE_WAKEUP Detection of a SUSPEND state upstream RESUME sent 15.9 USB Interrupt System 15.9.1 Interrupt System Priorities Figure 15-15. USB Interrupt Control System D+ USB Controller D- AT8xC51SND1C 96 USB Controller Init ...
Page 97
Table 1. Priority Levels 15.9.2 USB Interrupt Control System As shown in Figure 15-16, many events can produce a USB interrupt: • TXCMPL: Transmitted In Data Host accept a In packet. • RXOUTB0: Received Out Data Bank 0 when an ...
Page 98
Figure 15-16. USB Interrupt Control Block Diagram Endpoint 0..2) TXCMP UEPSTAX.0 RXOUTB0 UEPSTAX.1 RXOUTB1 UEPSTAX.6 RXSETUP UEPSTAX.2 STLCRC UEPSTAX.3 NAKOUT UEPCONX.5 NAKIN UEPCONX.4 NAKIEN UEPCONX.6 WUPCPU USBINT.5 EWUPCPU USBIEN.5 EORINT USBINT.4 EEORINT USBIEN.4 SOFINT USBINT.3 ESOFINT USBIEN.3 ...
Page 99
Reset Value = 0000 0000b Table 92. USBADDR Register USBADDR (S:C6h) – USB Address Register 4109L–8051–02/08 Bit Bit Number Mnemonic Description USB Enable Bit Set this bit to enable the USB controller. 7 USBE Clear this bit to disable and ...
Page 100
Reset Value = 0000 0000b Table 93. USBINT Register USBINT (S:BDh) – USB Global Interrupt Register Reset Value = 0000 0000b Table 94. USBIEN Register USBIEN (S:BEh) – USB Global Interrupt Enable Register AT8xC51SND1C 100 Bit Bit Number Mnemonic Description ...
Page 101
Reset Value = 0001 0000b Table 95. UEPNUM Register UEPNUM (S:C7h) – USB Endpoint Number Reset Value = 0000 0000b Table 96. UEPCONX Register UEPCONX (S:D4h) – USB Endpoint X Control Register (X = EPNUM set in UEPNUM) 4109L–8051–02/08 Bit ...
Page 102
Reset Value = 1000 0000b Table 97. UEPSTAX Register UEPSTAX (S:CEh) – USB Endpoint X Status and Control Register (X = EPNUM set in UEPNUM AT8xC51SND1C 102 Bit Bit Number Mnemonic Description Endpoint Enable Bit Set to enable the endpoint ...
Page 103
Bit Bit Number Mnemonic Description Control Endpoint Direction Bit This bit is relevant only if the endpoint is configured in Control type. Set for the data stage. Clear otherwise. 7 DIR Note: This bit should be configured on RXSETUP ...
Page 104
Reset Value = 0000 0000b Table 98. UEPRST Register UEPRST (S:D5h) – USB Endpoint FIFO Reset Register AT8xC51SND1C 104 Bit Bit Number Mnemonic Description Stall Handshake Request Bit 5 STALLRQ Set to send a STALL answer to the host for ...
Page 105
Reset Value = 0000 0000b Table 99. UEPIEN Register UEPIEN (S:C2h) – USB Endpoint Interrupt Enable Register Reset Value = 0000 0000b Table 100. UEPINT Register UEPINT (S:F8h Read-only) – USB Endpoint Interrupt Register 4109L–8051–02/08 Bit Bit Number Mnemonic Description ...
Page 106
Reset Value = 0000 0000b Table 101. UEPDATX Register UEPDATX (S:CFh) – USB Endpoint X FIFO Data Register (X = EPNUM set in UEPNUM) Reset Value = XXh Table 102. UBYCTX Register UBYCTX (S:E2h) – USB Endpoint X Byte Count ...
Page 107
Reset Value = 0000 0000b Table 103. UFNUML Register UFNUML (S:BAh, Read-only) – USB Frame Number Low Register Reset Value = 00h Table 104. UFNUMH Register UFNUMH (S:BBh, Read-only) – USB Frame Number High Register Reset Value = 00h 4109L–8051–02/08 ...
Page 108
Table 105. USBCLK Register USBCLK (S:EAh) – USB Clock Divider Register Reset Value = 0000 0000b AT8xC51SND1C 108 Bit Bit Number Mnemonic Description Reserved The value read from these bits ...
Page 109
MultiMedia Card Controller The AT8xC51SND1C implements a MultiMedia Card (MMC) controller. The MMC is used to store MP3 encoded audio files in removable Flash memory cards that can be easily plugged or removed from the application. 16.1 Card Concept ...
Page 110
The bus communication uses a special protocol (MultiMedia Card bus protocol) which is applica- ble for all devices. Therefore, the payload data transfer between the host and the cards can be bi-directional. 16.2.1 Bus Lines The MultiMedia Card bus architecture ...
Page 111
Figure 16-1. Sequential Read Operation MCMD MDAT Figure 16-2. (Multiple) Block Read Operation MCMD Command MDAT Block Read Operation As shown in Figure 16-3 and Figure 16-4 the data write operation uses a simple busy signalling of the write operation ...
Page 112
Command Token Format As shown in Figure 16-6, commands have a fixed code length of 48 bits. Each command token is preceded by a Start bit: a low level on MCMD line and succeeded by an End bit: a ...
Page 113
Table 107. R1 Response Format (Normal Response) Table 108. R2 Response Format (CID and CSD registers) Table 109. R3 Response Format (OCR Register) Table 110. R4 Response Format (Fast I/O) Table 111. R5 Response Format 16.2.5 Data Packet Format There ...
Page 114
CRC protection is not included in this case. The CRC protection algorithm for block data is a 16-bit CCITT polynomial. Figure 16-8. Data Token Format 16.2.6 Clock Control The MMC bus clock signal can be used by ...
Page 115
Figure 16-10 shows the external components to add for connecting a MMC card to the AT8xC51SND1C. MDAT and MCMD signals are connected to pull-up resistors. Value of these resistors is detailed in the Section “DC Characteristics”, page ...
Page 116
Figure 16-12. Configuration Flow 16.5 Command Line Controller As shown in Figure 16-13, the command line controller is divided in 2 channels: the command transmitter channel that handles the command transmission to the card through the MCMD line and the ...
Page 117
CRCDIS bit in MMCON0 register to indicate whether the CRC7 included in the response will be computed or not. In order to avoid CRC error, CRCDIS may be set for response that do not include CRC7. Figure 16-14 summarizes ...
Page 118
Figure 16-15. Data Line Controller Block Diagram MMINT.0 MMINT.2 F1EI F1FI 8-Byte TX Pointer FIFO 1 DTPTR MMCON0.6 16-Byte FIFO MMDAT RX Pointer DRPTR 8-Byte MMCON0.7 FIFO 2 F2EI F2FI MMINT.1 MMINT.3 16.6.1 FIFO Implementation The 16-Byte FIFO is based ...
Page 119
Figure 16-16. Data Controller Configuration Flows 16.6.3 Data Transmitter 16.6.3.1 Configuration For transmitting data to the card user must first configure the data controller in transmission mode by setting the DATDIR bit in MMCON1 register. Figure 16-17 summarizes the data ...
Page 120
CBUSY toggles, i.e. when the card enters and exits its busy state. This flag may generate an MMC interrupt request as detailed in Section "Interrupt", page 123. Figure 16-17. Data Stream Transmission Flows Data Stream ...
Page 121
Figure 16-18. Data Block Transmission Flows Data Block Transmission FIFOs Filling write 16 data to MMDAT Start Transmission DATEN = 1 DATEN = 0 FIFO Empty? F1EI or F2EI = 1? FIFO Filling write 8 data to MMDAT No More ...
Page 122
DCR bit in MMCON2 register. This time-out may be disarmed after receiving 8 data (F1FI flag set) or after receiving end of frame (EOFI flag ...
Page 123
Figure 16-20. Data Block Reception Flows Data Block Reception Start Transmission DATEN = 1 DATEN = 0 FIFO Full? F1EI or F2EI = 1? FIFO Reading read 8 data from MMDAT No More Data To Receive? a. Polling mode 16.6.5 ...
Page 124
The interrupt request is generated each time an unmasked flag is set, and the global MMC con- troller interrupt enable bit is set (EMMC in IEN1 register). Reading the MMINT register automatically clears the interrupt flags (acknowledgment). This implies that ...
Page 125
Reset Value = 0000 0000b 16.8.0.1 Table 114. MMCON1 Register MMCON1 (S:E5h) – MMC Control Register 1 Reset Value = 0000 0000b 4109L–8051–02/08 Bit Bit Number Mnemonic Description Data Transmit Pointer Reset Bit 6 DTPTR Set to reset the write ...
Page 126
Table 115. MMCON2 Register MMCON2 (S:E6h) – MMC Control Register 2 Reset Value = 0000 0000b 16.8.0.3 Table 116. MMSTA Register MMSTA (S:DEh Read Only) – MMC Control and Status Register AT8xC51SND1C 126 MMCEN DCR CCR ...
Page 127
Reset Value = 0000 0000b 16.8.0.4 Table 117. MMINT Register MMINT (S:E7h Read Only) – MMC Interrupt Register 4109L–8051–02/08 Bit Bit Number Mnemonic Description CRC16 Status Bit Transmission mode Set by hardware when the token response reports a good CRC. ...
Page 128
Reset Value = 0000 0011b 16.8.0.5 Table 118. MMMSK Register MMMSK (S:DFh) – MMC Interrupt Mask Register AT8xC51SND1C 128 Bit Bit Number Mnemonic Description End of Response Interrupt Flag 6 EORI Set by hardware at the end of response reception. ...
Page 129
Reset Value = 1111 1111b 16.8.0.6 Table 119. MMCMD Register MMCMD (S:DDh) – MMC Command Register Reset Value = 1111 1111b 16.8.0.7 Table 120. MMDAT Register MMDAT (S:DCh) – MMC Data Register Reset Value = 1111 1111b 16.8.0.8 Table 121. ...
Page 130
Reset Value = 0000 0000b AT8xC51SND1C 130 Bit Bit Number Mnemonic Description MMC Clock Divider MMCD7:0 8-bit divider for MMC clock generation. 4109L–8051–02/08 ...
Page 131
IDE/ATAPI Interface The AT8xC51SND1C provides an IDE/ATAPI interface allowing connection of devices such as CD-ROM reader, CompactFlash cards, Hard Disk Drive, etc. It consists of a 16-bit data transfer (read or write) between the AT8xC51SND1C and the IDE device. ...
Page 132
Figure 17-2. IDE Write Waveforms Notes: 17.1.1 IDE Device Connection Figure 17-3 and Figure 17-4 show 2 examples on how to interface IDE devices to the AT8xC51SND1C. In both examples P0 carries IDE low order data bits ...
Page 133
Table 122. External Data Memory Interface Signals 17.2 Registers Table 123. DAT16H Register DAT16H (S:F9h) – Data 16 High Order Byte Reset Value =XXXX XXXXb 4109L–8051–02/08 Signal Name Type Description Address Lines A15:8 I/O Upper address lines for the external ...
Page 134
Serial I/O Port The serial I/O port in the AT8xC51SND1C provides both synchronous and asynchronous com- munication modes. It operates as a Synchronous Receiver and Transmitter in one single mode (Mode 0) and operates as an Universal Asynchronous Receiver ...
Page 135
Figure 18-1. Timer 1 Baud Rate Generator Block Diagram 18.2.2 Internal Baud Rate Generator When using the Internal Baud Rate Generator, the Baud Rate is derived from the overflow of the timer. As shown in Figure 18-2 the Internal Baud ...
Page 136
Figure 18-3. Serial I/O Port Block Diagram (Mode 0) 18.3.1 Transmission (Mode 0) To start a transmission mode 0, write to SCON register clearing bits SM0, SM1. As shown in Figure 18-4, writing the Byte to transmit to SBUF register ...
Page 137
Baud Rate Selection (Mode 0) In mode 0, the baud rate can be either, fixed or variable. As shown in Figure 18-6, the selection is done using M0SRC bit in BDRCON register. Figure 18-7 gives the baud rate calculation ...
Page 138
Figure 18-9. Data Frame Format (Mode 1) 18.4.0.2 Modes 2 and 3 Modes 2 and 3 are full-duplex, asynchronous modes. The data frame (see Figure 18-10) con- sists of 11 bits: one start bit, eight data bits (transmitted and received ...
Page 139
Baud Rate Selection (Modes 1 and 3) In modes 1 and 3, the Baud Rate is derived either from the Timer 1 or the Internal Baud Rate Generator and allows different baud rate in reception and transmission. As shown ...
Page 140
MHz PER Baud Rate SPD SMOD1 BRL 9600 1 1 178 4800 1 1 100 Notes: 1. These frequencies are achieved in X1 mode These frequencies are achieved in X2 mode, F 18.4.5 Baud Rate ...
Page 141
Automatic Address Recognition The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set). Implemented in hardware, automatic address recognition enhances the multiprocessor commu- nication feature by allowing the ...
Page 142
Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don’t-care bits, e.g.: SADDR = 0101 0110b SADEN = 1111 1100b (SADDR | SADEN)=1111 111Xb The use of ...
Page 143
Figure 18-16. Serial I/O Interrupt System Figure 18-17. Interrupt Waveforms SMOD0 = X SMOD0 = 1 SMOD0 = 0 SMOD0 = 1 SMOD0 = 1 18.8 Registers Table 126. SCON Register SCON (S:98h) – Serial Control Register 4109L–8051–02/08 SCON.0 RI ...
Page 144
Reset Value = 0000 0000b Table 127. SBUF Register SBUF (S:99h) – Serial Buffer Register Reset value = XXXX XXXXb Table 128. SADDR Register AT8xC51SND1C 144 Bit Bit Number Mnemonic Description Framing Error Bit To select this function, set SMOD0 ...
Page 145
SADDR (S:A9h) – Slave Individual Address Register Reset Value = 0000 0000b Table 129. SADEN Register SADEN (S:B9h) – Slave Individual Address Mask Byte Register Reset Value = 0000 0000b Table 130. BDRCON Register BDRCON (S:92h) – Baud Rate Generator ...
Page 146
Table 131. BRL Register BRL (S:91h) – Baud Rate Generator Reload Register Reset Value = 0000 0000b AT8xC51SND1C 146 BRL7 BRL6 BRL5 BRL4 Bit Bit Number Mnemonic Description BRL7:0 Baud Rate Reload Value 4 ...
Page 147
Synchronous Peripheral Interface The AT8xC51SND1C implements a Synchronous Peripheral Interface with master and slave modes capability. Figure 19-1 shows an SPI bus configuration using the AT8xC51SND1C as master connected to slave peripherals while Figure 19-2 shows an SPI bus ...
Page 148
Description The SPI controller interfaces with the C51 core through three special function registers: SPCON, the SPI control register (see Table 133); SPSTA, the SPI status register (see Table 134); and SPDAT, the SPI data register (see Table 135). ...
Page 149
When the AT8xC51SND1C is the only slave on the bus, it can be useful not to use SS pin and get it back to I/O functionality. This is achieved by setting SSDIS bit in SPCON. This bit has no effect ...
Page 150
For simplicity, Figure 19-5 and Figure 19-6 depict the SPI waveforms in idealized form and do not provide precise timing information. For timing parameters refer to the Section “AC Characteristics”. Note: Figure 19-5. Data Transmission Format (CPHA = 0) SCK ...
Page 151
Figure 19-7. SS Timing Diagram 19.1.6 Error Conditions The following flags signal the SPI error conditions: • MODF in SPSTA signals a mode fault. MODF flag is relevant only in master mode when SS usage is enabled (SSDIS bit cleared). ...
Page 152
Slave Configuration The SPI operates in slave mode when the MSTR bit in SPCON is cleared and data has been loaded is SPDAT. 19.3.3 Data Exchange There are 2 possible methods to exchange data in master and slave modes: ...
Page 153
Figure 19-9. Master SPI Polling Flows 19.3.5 Master Mode with Interrupt Figure 19-10 shows the initialization phase and the transfer phase flows using the interrupt. Using this flow prevents any overrun error occurrence. The bit rate is selected according to ...
Page 154
Figure 19-10. Master SPI Interrupt Flows 19.3.6 Slave Mode with Polling Policy Figure 19-11 shows the initialization phase and the transfer phase flows using the polling. The transfer format depends on the master controller. SPIF flag is cleared when reading ...
Page 155
Figure 19-11. Slave SPI Polling Flows 19.3.7 Slave Mode with Interrupt Policy Figure 19-10 shows the initialization phase and the transfer phase flows using the interrupt. The transfer format depends on the master controller. Reading SPSTA at the beginning of ...
Page 156
Figure 19-12. Slave SPI Interrupt Policy Flows 19.4 Registers Table 133. SPCON Register SPCON (S:C3h) – SPI Control Register AT8xC51SND1C 156 SPI Initialization Interrupt Policy Select Slave Mode MSTR = 0 Select Format program CPOL & CPHA Enable interrupt ESPI ...
Page 157
Reset Value = 0001 0100b Note: Table 134. SPSTA Register SPSTA (S:C4h) – SPI Status Register Reset Value = 00000 0000b Table 135. SPDAT Register SPDAT (S:C5h) – Synchronous Serial Data Register Reset Value = XXXX XXXXb 4109L–8051–02/08 Bit Bit ...
Page 158
Two-wire Interface (TWI) Controller The AT8xC51SND1C implements a TWI controller supporting the four standard master and slave modes with multimaster capability. Thus, it allows connection of slave devices like LCD controller, audio DAC, etc., but also external master controlling ...
Page 159
Figure 20-2. Complete Data Transfer on TWI Bus SDA MSB Slave Address SCL 1 S The four operating modes are: • Master transmitter • Master receiver • Slave transmitter • Slave receiver Data transfer in each mode of operation are ...
Page 160
Table 136. Serial Clock Rates Note: 20.1.2 Master Transmitter Mode In the master transmitter mode, a number of data Bytes are transmitted to a slave receiver (see Figure 20-3). Before the master transmitter mode can be entered, SSCON must be ...
Page 161
When the slave address and the direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag is set again and a number of status code in SSSTA are possible. There are 40h, 48h or ...
Page 162
If the SSAA bit is reset during a transfer, the controller will transmit the last Byte of the transfer and enter state C0h or C8h. The controller is switched to the not addressed slave mode and will ignore the master ...
Page 163
Figure 20-3. Format and States in the Master Transmitter Mode Successful transmis- S sion to a slave receiver 08h Next transfer started with a repeated start condition Not acknowledge received after the slave address Not acknowledge received after a data ...
Page 164
Figure 20-4. Format and States in the Master Receiver Mode Successful reception S from a slave transmitter 08h Next transfer started with a repeated start condition Not acknowledge received after the slave address Arbitration lost in slave address or data ...
Page 165
Figure 20-5. Format and States in the Slave Receiver Mode Reception of the own slave address and one or more data Bytes. All are acknowledged Last data Byte received is not acknowledged Arbitration lost as master and addressed as slave ...
Page 166
Figure 20-6. Format and States in the Slave Transmitter Mode Reception of the own slave address and transmission of one or more data Bytes. Arbitration lost as master and addressed as slave Last data Byte transmitted. Switched to not addressed ...
Page 167
Table 137. Status for Master Transmitter Mode Status Code Status of the TWI Bus SSSTA and TWI Hardware To/From SSDAT A START condition has 08h Write SLA+W been transmitted Write SLA+W A repeated START 10h condition has been transmitted Write ...
Page 168
Table 138. Status for Master Receiver Mode Status Code Status of the TWI Bus SSSTA and TWI Hardware To/From SSDAT A START condition has 08h Write SLA+R been transmitted Write SLA+R A repeated START 10h condition has been transmitted Write ...
Page 169
Table 139. Status for Slave Receiver Mode with Own Slave Address Status Code Status of the TWI Bus SSSTA and TWI Hardware To/From SSDAT No SSDAT action Own SLA+W has been 60h received; ACK has been returned No SSDAT action ...
Page 170
Table 140. Status for Slave Receiver Mode with General Call Address Status Code Status of the TWI Bus SSSTA and TWI Hardware To/From SSDAT General call address No SSDAT action has been received; 70h ACK has been No SSDAT action ...
Page 171
Table 141. Status for Slave Transmitter Mode Status of the TWI Bus Status and TWI Hardware Code SSSTA To/From SSDAT Write data Byte Own SLA+R has been A8h received; ACK has been returned Write data Byte Arbitration lost in Write ...
Page 172
Registers Table 143. SSCON Register SSCON (S:93h) – Synchronous Serial Control Register Reset Value = 0000 0000b Table 144. SSSTA Register SSSTA (S:94h) – Synchronous Serial Status Register AT8xC51SND1C 172 SSCR2 SSPE SSSTA SSSTO Bit Bit ...
Page 173
Reset Value = F8h Table 145. SSDAT Register SSDAT (S:95h) – Synchronous Serial Data Register Reset Value = 1111 1111b Table 146. SSADR Register SSADR (S:96h) – Synchronous Serial Address Register Reset Value = 1111 1110b 4109L–8051–02/08 Bit Bit Number ...
Page 174
Analog to Digital Converter The AT8xC51SND1C implement a 2-channel 10-bit (8 true bits) analog to digital converter (ADC). First channel of this ADC can be used for battery monitoring while the second one can be used for voice sampling ...
Page 175
Figure 21-2. Timing Diagram 21.1.1 Clock Generator The ADC clock is generated by division of the peripheral clock (see details in section “X2 Fea- ture”, page 13). The division factor is then given by ADCP4:0 bits in ADCLK register. Figure ...
Page 176
Section "End Of Conversion", page 176). This bit is cleared by hardware at the end of the conversion. Notes: 21.1.4 Configuration The ADC configuration consists in programming the ADC clock as detailed in the Section "Clock Generator", page ...
Page 177
EADC bit in IEN1 register. This flag is set by hardware and must be reset by software. 21.2 Registers Table 148. ADCON Register ADCON (S:F3h) – ADC Control Register Reset Value = 0000 0000b Table 149. ADCLK ...
Page 178
Table 150. ADDH Register ADDH (S:F5h Read Only) – ADC Data High Byte Register Reset Value = 0000 0000b Table 151. ADDL Register ADDL (S:F4h Read Only) – ADC Data Low Byte Register Reset Value = 0000 0000b AT8xC51SND1C 178 ...
Page 179
Keyboard Interface The AT8xC51SND1C implement a keyboard interface allowing the connection matrix keyboard based on 4 inputs with programmable interrupt capability on both high or low level. These inputs are available as ...
Page 180
KBCON (S:A3h) – Keyboard Control Register Reset Value = 0000 1111b 22.2.0.1 Table 153. KBSTA Register KBSTA (S:A4h) – Keyboard Control and Status Register Reset Value = 0000 0000b AT8xC51SND1C 180 KINL3 KINL2 KINL1 KINL0 Bit Bit ...
Page 181
Electrical Characteristics 23.1 Absolute Maximum Rating Storage Temperature ......................................... -65 to +150°C Voltage on any other Pin .................................... I per I/O Pin ................................................................. Power Dissipation ............................................................. 1 W Operating Conditions Ambient Temperature Under ...
Page 182
... AT83SND1C I DL Idle Mode Current AT80C51SND1C Idle Mode Current AT89C51SND1C Power-Down Mode Current AT83SND1C I PD Power-Down Mode Current AT80C51SND1C Power-Down Mode Current AT89C51SND1C I FP Flash Programming Current Notes: Table 155. Typical Reference Design AT89C51SND1C Power Consumption Player Mode Stop Playing AT8xC51SND1C ...
Page 183
I I and I Test Conditions DD Figure 23-1. I Figure 23-2. I Figure 23-3. I 4109L–8051–02/08 Test Condition, Active Mode DD VDD RST (NC) X2 Clock Signal X1 VSS PVSS UVSS AVSS VSS All other pins ...
Page 184
Converter Table 156 Converter DC Characteristics V = 2 Symbol REF R REF C IA 23.2.3 Oscillator & Crystal ...
Page 185
Phase Lock Loop 23.2.4.1 Schematic Figure 23-5. PLL Filter Connection 23.2.4.2 Parameters Table 158. PLL Filter Characteristics V = 2 Symbol 23.2.5 USB Connection 23.2.5.1 Schematic Figure 23-6. USB Connection 23.2.5.2 ...
Page 186
MMC Controller 23.2.6.1 Schematic Figure 23-7. MMC Connection 23.2.6.2 Parameters Table 160. MMC Components Characteristics V = 2 Symbol R CMD R DAT 23.2.7 In System Programming 23.2.7.1 Schematic Figure 23-8. ISP Pull-Down Connection ...
Page 187
AC Characteristics 23.3.1 External Program Bus Cycles 23.3.1.1 Definition of Symbols Table 162. External Program Bus Cycles Timing Symbol Definitions 23.3.1.2 Timings Test conditions: capacitive load on all pins= 50 pF. Table 163. External Program Bus Cycle - Read ...
Page 188
Waveforms Figure 23-9. External Program Bus Cycle - Read Waveforms 23.3.2 External Data 8-bit Bus Cycles 23.3.2.1 Definition of Symbols Table 164. External Data 8-bit Bus Cycles Timing Symbol Definitions 23.3.2.2 Timings Test conditions: capacitive load on all pins= ...
Page 189
Table 166. External Data 8-bit Bus Cycle - Write AC Timings V = 2 4109L–8051–02/08 Symbol Parameter T RD Pulse Width RLRH T RD high to ALE High RHLH T Address Valid to Valid Data ...
Page 190
Waveforms Figure 23-10. External Data 8-bit Bus Cycle - Read Waveforms Figure 23-11. External Data 8-bit Bus Cycle - Write Waveforms 23.3.3 External IDE 16-bit Bus Cycles 23.3.3.1 Definition of Symbols Table 167. External IDE 16-bit Bus Cycles Timing ...
Page 191
Timings Test conditions: capacitive load on all pins= 50 pF. Table 168. External IDE 16-bit Bus Cycle - Data Read AC Timings V = 2 Table 169. External IDE 16-bit Bus Cycle - Data ...
Page 192
Waveforms Figure 23-12. External IDE 16-bit Bus Cycle - Data Read Waveforms Note: Figure 23-13. External IDE 16-bit Bus Cycle - Data Write Waveforms Note: 23.4 SPI Interface 23.4.0.4 Definition of Symbols Table 170. SPI Interface Timing Symbol Definitions ...
Page 193
Timings Test conditions: capacitive load on all pins= 50 pF. Table 171. SPI Interface Master AC Timing V = 2 Note: 4109L–8051–02/08 = -40 to +85°C A Symbol Parameter T Clock Period CHCH T ...
Page 194
Waveforms Figure 23-14. SPI Slave Waveforms (SSCPHA= 0) (input) SCK (SSCPOL= 0) (input) SCK (SSCPOL= 1) (input) MISO (output) MOSI (input) Note: Figure 23-15. SPI Slave Waveforms (SSCPHA (input) SCK (SSCPOL= 0) (input) SCK (SSCPOL= 1) (input) ...
Page 195
Figure 23-16. SPI Master Waveforms (SSCPHA (output) SCK (SSCPOL= 0) (output) SCK (SSCPOL= 1) (output) MOSI (input) MISO (output) Note: Figure 23-17. SPI Master Waveforms (SSCPHA (output) SCK (SSCPOL= 0) (output) SCK (SSCPOL= 1) (output) MOSI ...
Page 196
V = 2 Notes: 23.4.1.2 Waveforms Figure 23-18. Two Wire Waveforms START or Repeated START condition SDA (INPUT/OUTPUT) SCL (INPUT/OUTPUT) AT8xC51SND1C 196 = -40 to +85°C A Symbol Parameter T ; STA Start condition hold ...
Page 197
MMC Interface 23.4.2.1 Definition of symbols Table 173. MMC Interface Timing Symbol Definitions 23.4.2.2 Timings Table 174. MMC Interface AC timings V = 2 23.4.2.3 Waveforms Figure 23-19. MMC Input-Output Waveforms 4109L–8051–02/08 Signals C ...
Page 198
Audio Interface 23.4.3.1 Definition of symbols Table 175. Audio Interface Timing Symbol Definitions 23.4.3.2 Timings Table 176. Audio Interface AC timings V = 2 Note: 23.4.3.3 Waveforms Figure 23-20. Audio Interface Waveforms AT8xC51SND1C 198 ...
Page 199
Analog to Digital Converter 23.4.4.1 Definition of symbols Table 177. Analog to Digital Converter Timing Symbol Definitions 23.4.4.2 Characteristics Table 178. Analog to Digital Converter AC Characteristics V = 2 Notes: 4109L–8051–02/08 Signals C ...
Page 200
Waveforms Figure 23-21. Analog to Digital Converter Internal Waveforms CLK ADEN Bit ADSST Bit Figure 23-22. Analog to Digital Converter Characteristics AT8xC51SND1C 200 T CLCL T EHSH Code Out 1023 1022 1021 1020 1019 1018 Ideal Transfer curve 7 ...