AT80C51SND1C-ROTUL Atmel, AT80C51SND1C-ROTUL Datasheet - Page 61

• Manufacturer Part Number: AT80C51SND1C-ROTUL
• Description: IC MCU FLASH MP3 DECODER 80-TQFP
• Manufacturer: Atmel
• Series: 80Cr

Specifications of AT80C51SND1C-ROTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Type: ROMless
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

12. Watchdog Timer
12.1
Figure 12-1. WDT Block Diagram
12.2
Figure 12-2. WDT Clock Controller and Symbol
4109L–8051–02/08
Description
Watchdog Clock Controller
System Reset
CLOCK
WDT
CLOCK
CLOCK
OSC
PER
The AT8xC51SND1C implement a hardware Watchdog Timer (WDT) that automatically resets
the chip if it is allowed to time out. The WDT provides a means of recovering from routines that
do not complete successfully due to software or hardware malfunctions.
The WDT consists of a 14-bit prescaler followed by a 7-bit programmable counter. As shown in
Figure 12-1, the 14-bit prescaler is fed by the WDT clock detailed in Section “Watchdog Clock
Controller”, page 61.
The Watchdog Timer Reset register (WDTRST, see Table 68) provides control access to the
WDT, while the Watchdog Timer Program register (WDTPRG, see Figure 12-4) provides time-
out period programming.
Three operations control the WDT:
•
•
•
As shown in Figure 12-2 the WDT clock (F
or the oscillator clock (F
issued from the Clock Controller block as detailed in Section "Clock Controller", page 13. When
WTX2 bit is set, the WDT clock frequency is fixed and equal to the oscillator clock frequency
divided by 2. When cleared, the WDT clock frequency is equal to the oscillator clock frequency
divided by 2 in standard mode or to the oscillator clock frequency in X2 mode.
RST
Chip reset clears and disables the WDT.
Programming the time-out value to the WDTPRG register.
Writing a specific 2-Byte sequence to the WDTRST register clears and enables the WDT.
÷ 6
1Eh-E1h Decoder
÷
2
WDTRST
CKCON.6
WTX2
0
1
RST
MATCH
14-bit Prescaler
EN
OSC
) depending on the WTX2 bit in CKCON register. These clocks are
WDT Clock
WDT
RST
CLOCK
) is derived from either the peripheral clock (F
OSC
7-bit Counter
WDTPRG.2:0
WTO2:0
SET
Pulse Generator
WDT Clock Symbol
OV
CLOCK
WDT
AT8xC51SND1C
To internal reset
RST
PER
61
)