AT91FR40162SB-CU-999 Atmel, AT91FR40162SB-CU-999 Datasheet - Page 10

• Manufacturer Part Number: AT91FR40162SB-CU-999
• Description: IC MCU 32BIT RISC 121BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91FR40162SB-CU-999

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 75MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: WDT
• Number Of I /o: 32
• Program Memory Size: 2MB (1M x 16)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-BGA
• Data Bus Width: 32 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

7. Product Overview
7.1
7.2
7.3
7.4
7.4.1
7.4.2
10
Power Supply
Input/Output Considerations
Master Clock
Reset
AT91FR40162SB
NRST Pin
Watchdog Reset
The AT91FR40162SB device has two types of power supply pins:
An independent I/O supply allows a flexible adaptation to external component signal levels.
The AT91FR40162SB I/O pads accept voltage levels up to the VDDIO power supply limit. After
the reset, the microcontroller peripheral I/Os are initialized as inputs to provide the user with
maximum flexibility. It is recommended that in any application phase, the inputs to the microcon-
troller be held at valid logic levels to minimize the power consumption.
The AT91FR40162SB has a fully static design and works on the Master Clock (MCK), provided
on the MCKI pin from an external source.
The Master Clock is also provided as an output of the device on the pin MCKO, which is multi-
plexed with a general purpose I/O line. While NRST is active, and after the reset, the MCKO is
valid and outputs an image of the MCK signal. The PIO Controller must be programmed to use
this pin as standard I/O line.
Reset restores the default states of the user interface registers (defined in the user interface of
each peripheral), and forces the ARM7TDMI to perform the next instruction fetch from address
zero. Except for the program counter the ARM7TDMI registers do not have defined reset states.
NRST is an active low-level input. It is asserted asynchronously, but exit from reset is synchro-
nized internally to the MCK. The signal presented on MCKI must be active within the
specification for a minimum of 10 clock cycles up to the rising edge of NRST to ensure correct
operation. The first processor fetch occurs 80 clock cycles after the rising edge of NRST.
The watchdog can be programmed to generate an internal reset. In this case, the reset has the
same effect as the NRST pin assertion, but the pins BMS and NTRI are not sampled. Boot Mode
and Tri-state Mode are not updated. If the NRST pin is asserted and the watchdog triggers the
internal reset, the NRST pin has priority.
• VDDCORE pins that power the chip core (i.e., the AT91R40008 with its embedded SRAM
• VDDIO pins that power the AT91R40008 I/O lines and the Flash memory
and peripherals)
6410BS–ATARM–12-Jan-10