Z86D7308PSC1987 Zilog, Z86D7308PSC1987 Datasheet
Z86D7308PSC1987
Specifications of Z86D7308PSC1987
Related parts for Z86D7308PSC1987
Z86D7308PSC1987 Summary of contents
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... Z86D73 40/44/48-Pin Low-Voltage IR OTP Preliminary Product Specification PS019401-1102 ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126-3432 Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com ...
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... Telephone: 408.558.8500 Fax: 408.558.8300 www.ZiLOG.com ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. Document Disclaimer ©2002 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded ...
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1. Counter/Timers Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 35. SCLK Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Features Table 1 shows the features of the Z86D73. Table 1. Features Device OTP (KB) RAM* (Bytes) I/O Lines Voltage Range Z86D73 32 Note: *General purpose • Low power consumption–40 mW (typical) • Three standby modes – Stop—2 A (typical) ...
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... CC General Description The Z86D73 is an OTP-based member of the MCU family of IR (infrared) micro- controllers. With 237 bytes of general-purpose RAM and ROM, ZiLOG’s CMOS microcontrollers offer fast executing, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, automated pulse generation/ reception, and internal key-scan pull-up transistors. ...
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Note: All signals with an overline, “ ”, are active Low. For example, B/W, in which WORD is active Low, and B/W, in which BYTE is active Low. Power connections use the conventional descriptions listed in Table 2. Table 2. ...
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Figure 2. Functional Block Diagram PS019401-1102 40/44/48-Pin Low-Voltage IR OTP Z86D73 ...
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Pin Description The pins are shown in Figure 3, Figure 4, Figure 5, and Figure 6. The pins are described in Table 3. 1 R/W P25 P26 P27 P04 P05 P06 P14 P15 P07 VDD P16 P17 XTAL2 XTAL1 P31 ...
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P21 34 P22 P23 P24 DS R/RL R/W P25 P26 P27 P04 44 1 Figure 4. 44-Pin QFP Pin Assignment 6 7 P21 P22 P23 P24 DS R/RL R/W P25 P26 P27 17 P04 18 Figure 5. 44-Pin PLCC ...
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XTAL2 XTAL1 Figure 6. 48-Pin SSOP Assignment Table 3. Pin Identification 40-Pin DIP # PS019401-1102 R/W 1 ROM/ROMLESS 48 P25 DS P26 P24 P27 P23 P04 P22 N/C P21 P05 P20 ...
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Table 3. Pin Identification (Continued) 40-Pin DIP # PS019401-1102 40/44/48-Pin Low-Voltage ...
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Table 3. Pin Identification (Continued) 40-Pin DIP # 31 25 Absolute Maximum Ratings Stresses greater than those listed in Table 4 might cause permanent damage to the device. This rating is a stress rating only. Functional operation of the device ...
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Standard Test Conditions The characteristics listed in this product specification apply for standard test con- ditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (see Figure 7). Figure 7. Test Load Diagram Capacitance ...
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DC Characteristics Table 6. DC Characteristics Sym Parameter Max Input Voltage V Clock Input High Voltage CH V Clock Input Low Voltage CL V Input High Voltage IH V Input Low Voltage IL V Output High Voltage OH1 V Output ...
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Table 6. DC Characteristics (Continued) Sym Parameter I Output Leakage OL I Supply Current CC I Standby Current (HALT CC1 Mode) I Standby Current (STOP CC2 Mode) Note: WDT, Comparators, Low Voltage Detection, and ADC (if applicable are disabled. The ...
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AC Characteristics Figure 9 and Table 8 describe the external I/O or memory read and write timing. Figure 8. External I/O or Memory Read/Write Timing PS019401-1102 40/44/48-Pin Low-Voltage IR OTP Z86D73 ...
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Table 7. External I/O or Memory Read and Write Timing (Preliminary) No Symbol Parameter 1 TdA(AS) Address Valid to AS Rising Delay 2 TdAS(A) AS Rising to Address Float Delay 3 TdAS(DR) AS Rising to Read Data Required Valid 4 ...
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Table 7. External I/O or Memory Read and Write Timing (Preliminary) (Continued) No Symbol Parameter 17 TdAS(DS) AS Rising to DS Falling Delay 18 TdDM(AS) DM Valid to AS Falling Delay 19 TdDS(DM) DS Rise to DM Valid Delay 20 ...
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Clock IRQ N Clock Setup Stop Mode Recovery Source Figure 9. Additional Timing PS019401-1102 40/44/48-Pin Low-Voltage IR OTP ...
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Table 8. Additional Timing No Sym Parameter 1 TpC Input Clock Period 2 TrC,TfC Clock Input Rise and Fall Times 3 TwC Input Clock Width 4 TwTinL Timer Input Low Width 5 TwTinH Timer Input High Width 6 TpTin Timer ...
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Table 8. Additional Timing (Continued) No Sym Parameter 12 Twdt Watch-Dog Timer Delay Time Notes: 1. Timing Reference uses 0 Interrupt request through Port 3 (P33–P31). 3. Interrupt request through Port 3 (P30). 4. SMR – D5 ...
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XTAL1 Crystal 1 (Time-Based Input) This pin connects a parallel-resonant crystal, ceramic resonator, LC net- work to the on-chip oscillator input. Additionally, an optional external single-phase clock can be coded to the on-chip oscillator input. XTAL2 Crystal 2 ...
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An optional pull-up transistor is available as a mask option on all Port 0 bits with nibble select. Note: Internal pull-ups are disabled on any given pin or group of port pins when programmed into output mode. Z86D73 Open-Drain I/O ...
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... Port 1 (P17–P10) Port 1 (see Figure 11 multiplexed Address (A7–A0) and Data (D7–D0), CMOS-compatible port. Port 1 is dedicated to the ZiLOG ZBus ory interface. The operations of Port 1 are supported by the Address Strobe (AS) and Data Strobe (DS) lines and by the Read/Write (R/W) and Data Memory (DM) control lines ...
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Port 2 (P27–P20) Port 8-bit, bidirectional, CMOS-compatible I/O port (see Figure 12). These eight I/O lines can be independently configured under software control as inputs or outputs. Port 2 is always available for I/O operation. A mask ...
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Port 3 (P37–P31) Port 7-bit, CMOS-compatible fixed I/O port (see Figure 13). Port 3 consists of three fixed input (P33–P31) and four fixed output (P37–P34), which can be con- figured under software control for interrupt and as ...
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Two on-board comparators process analog signals on P31 and P32, with refer- ence to the voltage on Pref1 and P33. The analog function is enabled by program- ming the Port 3 Mode Register (bit 1). P31 and P32 are programmable ...
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CTR0, D0 P34 data MU T8_Out P31 + Pref 1 T16_Out T8/T16_Out P37 data P32 + Pref 2 Figure 14. Port 3 Counter/Timer Output Configuration PS019401-1102 PCON MUX - Comp 1 CTR2 Out 35 ...
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Comparator Inputs In analog mode, P31 and P32 have a comparator front end. The comparator refer- ence is supplied to P33 and Pref1. In this mode, the P33 internal data latch and its corresponding IRQ1 are diverted to the SMR ...
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Location of first byte of instruction executed after RESET Interrupt Vector (Lower Byte) Interrupt Vector (Upper Byte) Figure 15. Program Memory Map (32K OTP) PS019401-1102 Not Accessible 32768 On-Chip ROM 12 Reset Start Address IRQ5 11 10 IRQ5 9 IRQ4 ...
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Expanded Register File The register file has been expanded to allow for additional system control regis- ters and for mapping of additional peripheral devices into the register address area. The Z8 register address space (R0 through R15) has been implemented ...
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Register Pointer 7 6 Working Register Group Pointer Z8 Register File (Bank Expanded Reg. Bank/Group (0) Register ( ( ( ( ...
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The upper nibble of the register pointer (see Figure 17) selects which working reg- ister group bytes in the register file, is accessed out of the possible 256. The lower nibble selects the expanded register file bank and, ...
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LD RP, #0Dh LD RP, #7Dh LD 71h R1, 2 Register File The register file (bank 0) consists of 4 I/O port registers, 237 general-purpose reg- isters, 16 control and status registers (R0–R3, R4–R239, and R240–R255, respectively), and ...
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Stack The Z86D73 internal register file is used for the stack. An 8-bit Stack Pointer (R255) is used for the internal stack that resides in the general-purpose registers (R4–R239). SPH is used as a general-purpose register only when using internal ...
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Register Description LVD(D)0Ch Low-Voltage Detection Register Note: The LVD flag will be valid after enabling the detection for 20 S (design estimation, not tested in production). LVD does not work at STOP mode. It must be disabled during STOP mode ...
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HI16(D)09h This register holds the captured data from the output of the 16-bit Counter/ Timer16. This register holds the MS-Byte of the data. Field T16_Capture_HI 76543210 L016(D)08h This register holds the captured data from the output of the 16-bit Counter/ ...
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TC8L(D)04h Counter/Timer8 Low Hold Register Field T8_Level_LO CTR0 Counter/Timer8 Control Register Table 11 lists and briefly describes the fields for this register. Table 11. CTR0 (D)00 Counter/Timer8 Control Register Field Bit Position T8_Enable 7------- Single/Modulo-N -6------- Time_Out --5------ T8 _Clock ...
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Single/Modulo-N When set to 0 (modulo-n), the counter reloads the initial value when the terminal count is reached. When set to 1 (single pass), the counter stops when the terminal count is reached. Timeout This bit is set when T8 ...
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CTR1(D)01h This register controls the functions in common with the T8 and T16. Table 12 lists and briefly describes the fields for this register. Table 12. CTR(D)01h T8 and T16 Common Functions Field Bit Position Mode 7------- P36_Out/ -6------ Demodulator_Input ...
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Table 12. CTR(D)01h T8 and T16 Common Functions (Continued) Field Bit Position Initial_T16_Out/ -------0 Falling_Edge Note: *Default upon Power-On Reset Mode If the result is 0, the counter/timers are in the transmit mode; otherwise, they are in the demodulation mode. ...
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CTR1, D1. In Demodulation Mode, this bit is set to 1 when a rising edge is detected in the input signal. In order to ...
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Table 13. CTR2 (D)02h: Counter/Timer16 Control Register (Continued) Field Bit Position T16 _Clock ---43--- Capture_INT_Mask -----2-- Counter_INT_Mask ------1- P35_Out -------0 Note: *Indicates the value upon Power-On Reset. T16_Enable This field enables T16 when set to 1. Single/Modulo-N In Transmit Mode, ...
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Counter_INT_Mask Set this bit to allow an interrupt when T16 times out. P35_Out This bit defines whether P35 is used as a normal output pin or T16 output. SMR2 Stop-Mode Recovery Register 2 Table 14 lists and briefly describes the ...
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Counter/Timer Functional Blocks Input Circuit The edge detector monitors the input signal on P31 or P20. Based on CTR1 D5– D4, a pulse is generated at the Pos Edge or Neg Edge line when an edge is detected. Glitches in ...
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Reset T8_Enable Bit Set Timeout Status Bit (CTR0 D5) and Generate Timeout_Int if Enabled Figure 20. Transmit Mode Flowchart PS019401-1102 40/44/48-Pin Low-Voltage IR OTP T8 (8-Bit) Transmit Mode No T8_Enable Bit Set CTR0, D7 Yes 0 CTR1, D1 Value Load ...
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When T8 is enabled, the output T8_OUT switches to the initial value (CTR1, D1). If the initial value (CTR1, D1 TC8L is loaded; otherwise, TC8H is loaded into the counter. In Single-Pass Mode (CTR0, D6), T8 counts down ...
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The letter Note: Transition from 0 to Caution: Using the same instructions for stopping the counter/timers and setting the status bits is not recommended. Two successive commands are necessary. First, the counter/timers must be stopped. Second, the status bits must ...
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T8 Demodulation Mode Program TC8L and TC8H to falling, or both depending on CTR1, D5; D4) is detected, it starts to count down. When a subsequent edge (rising, falling, or both depending on CTR1, D5; D4) is detected during counting, ...
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Positive Figure 24. Demodulation Mode Count Capture Flowchart PS019401-1102 T8 (8-Bit) Count Capture T8 Enable (Set by User) No Yes Edge Present No Yes What Kind of Edge T8 LO8 T8 FFh ...
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Disable TC8 Figure 25. Demodulation Mode Flowchart PS019401-1102 40/44/48-Pin Low-Voltage IR OTP T8 (8-Bit) Demodulation Mode T8 Enable CTR0 Yes FFh TC8 First Edge Present No Yes Enable TC8 T8_Enable Bit Set No Yes No Edge Present Yes ...
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T16 Transmit Mode In Normal or Ping-Pong Mode, the output of T16 when not enabled, is dependent on CTR1, D0 T16_OUT T16_OUT is 0. You can force ...
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Caution: Do not load these registers at the time the values are to be loaded into the counter/timer to ensure known operation. An initial count not allowed. An initial count of 0 causes T16 to count from ...
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This T16 mode is generally used to measure space time, the length of time between bursts of carrier signal (marks CTR2 Is 1 T16 ignores the subsequent edges in the input signal and continues counting down. A ...
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Enable TC8 Enable TC16 Figure 29. Ping-Pong Mode Initiating Ping-Pong Mode First, make sure both counter/timers are not running. Set T8 into Single-Pass Mode (CTR0, D6), set T16 into Single-Pass Mode (CTR2, D6), and set the Ping- Pong Mode (CTR1, ...
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During Ping-Pong Mode The enable bits of T8 and T16 (CTR0, D7; CTR2, D7) are set and cleared alter- nately by hardware. The timeout bits (CTR0, D5; CTR2, D5) are set every time the counter/timers reach the terminal count. Interrupts ...
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IRQ Register D6, D7 IRQ2 Interrupt Request Figure 31. Interrupt Block Diagram PS019401-1102 40/44/48-Pin Low-Voltage IR OTP P31 P32 P33 Interrupt Edge Timer 16 Select IRQ0 IRQ1 IRQ3 IRQ IMR IPR Global Interrupt Enable Priority Logic Vector Select P R ...
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Table 15. Interrupt Types, Sources, and Vectors Name Source IRQ0 P32 IRQ1 P33 IRQ2 P31, T IRQ3 T16 IRQ4 T8 IRQ5 LVD When more than one interrupt is pending, priorities are resolved by a programma- ble priority encoder controlled by ...
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Clock The Z86D73 on-chip oscillator has a high-gain, parallel-resonant amplifier, for connection to a crystal, LC, ceramic resonator, or any suitable external clock source (XTAL1 = Input, XTAL2 = Output). The crystal must be AT cut, 1 MHz to 8 ...
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Power-On Reset (POR) A timer circuit clocked by a dedicated on-board RC oscillator is used for the Power-On Reset (POR) timer function. The POR time allows V tor circuit to stabilize before instruction execution begins. The POR timer circuit is ...
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Port Configuration Register (PCON) The PCON register (Figure 33) configures the comparator output on Port located in the expanded register 2 at Bank F, location 00. PCON (FH) 00H Default setting after reset ...
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Stop-Mode Recovery Register (SMR) This register selects the clock divide value and determines the mode of Stop- Mode Recovery (Figure 34). All bits are write only except bit 7, which is read only. Bit flag bit that ...
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SCLK/TCLK Divide-by-16 Select (D0 the SMR controls a divide-by-16 prescaler of SCLK/TCLK (Figure 35). The purpose of this control is to selectively reduce device power consumption during normal processor execution (SCLK control) and/or HALT Mode (where TCLK sources ...
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SMR VCC SMR P31 SMR P32 SMR P33 To IRQ1 S4 SMR P27 SMR P20 P23 SMR P20 P27 ...
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Table 17. Stop-Mode Recovery Source SMR:432 Note: Any Port 2 bit defined as an output drives the corresponding input to the default ...
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Stop-Mode Recovery Register 2 (SMR2) This register determines the mode of Stop-Mode Recovery for SMR2 (Figure 37). SMR2 (0F Note: If used in conjunction with SMR, either of the two specified events causes ...
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Watch-Dog Timer Mode Register (WDTMR) The WDT is a retriggerable one-shot timer that resets the reaches its termi- nal count. The WDT must initially be enabled by executing the WDT instruction. On subsequent executions of the WDT ...
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WDT Time Select (D0, D1) This bit selects the WDT time period configured as indicated in Table 18. Table 18. WDT Time Select Timeout of Internal RC OSC min ...
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Clock Filter CK Source Select (WDTMR) XTAL INTERNAL RC OSC. Low Operating V + Voltage Det. DD VBO/VLV - 2V REF. WDT From Stop Mode 12-ns Glitch Filter Recovery Source Stop Delay Select (SMR) * CLR1 and CLR2 enable ...
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Mask Selectable Options There are seven Mask Selectable Options to choose from based on ROM code requirements. These are listed in Table 19. Table 19. Mask Selectable Options RC/Other 32 kHz XTAL Port 00–03 Pull-Ups Port 04–07 Pull-Ups Port 10–13 ...
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Expanded Register File Control Registers (0D) The expanded register file control registers (0D) are shown in Figure 40 through Figure 43. CTR0 (0D Default setting after reset Figure 40. TC8 Control Register ((0D) OH: Read/Write ...
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CTR1 (0D Default setting after reset Figure 41. T8 and T16 Common Control Functions ((0D) 1h: Read/Write) PS019401-1102 Z86D73 40/44/48-Pin Low-Voltage ...
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Notes: Care must be taken in differentiating Transmit Mode from Demodulation Mode. Depending on which of these two modes is operating, the CTR1 bit has different functions. Changing from one mode to another cannot be done without disabling the counter/timers. ...
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LVD (0D) 0CH Default Figure 43. Low-Voltage Detection Note: Do not modify register P01M while checking a low-voltage condition. Switching noise of both ports 0 and 1 together might trigger the LVD flag. PS019401-1102 D4 D3 ...
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Expanded Register File Control Registers (0F) The expanded register file control registers (0F) are shown in Figure 44 through Figure 57. SMR (0F Default setting after reset * * Default setting after reset and stop-mode ...
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SMR2 (0F Note: If used in conjunction with SMR, either of the two specified events causes a Stop-Mode Recovery. * Default setting after reset * * At the XOR gate input Figure 45. ...
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WDTMR (0F Default setting after reset Figure 46. Watch-Dog Timer Register ((0F) 0Fh: Write Only) PS019401-1102 Z86D73 40/44/48-Pin Low-Voltage IR OTP ...
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PCON (FH) 00H Default setting after reset Figure 47. Port Configuration Register (PCON) ((0F) 0h: Write Only) R246 P2M Default setting after reset Figure 48. Port 2 Mode Register (F6h: Write Only) ...
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R247 P3M Default setting after reset Figure 49. Port 3 Mode Register (F7h: Write Only) PS019401-1102 Z86D73 40/44/48-Pin Low-Voltage IR OTP 0: ...
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R248 P01M Default setting after reset; only P00 and P07 are available on Z86L71 Figure 50. Port 0 and 1 Mode Register (F8h: Write Only) PS019401-1102 ...
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R249 IPR Figure 51. Interrupt Priority Register (F9h: Write Only) PS019401-1102 Z86D73 40/44/48-Pin Low-Voltage IR OTP Interrupt Group Priority 000 Reserved 001 C ...
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R250 IRQ Figure 52. Interrupt Request Register (FAh: Read/Write) R251 IMR Default setting after reset * * Only by using E1, D1 instruction required before changing the IMR register Figure 53. ...
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R252 Flags Figure 54. Flag Register (FCh: Read/Write) R253 Default setting after reset = 0000 0000 Figure 55. Register Pointer (FDh: Read/Write) PS019401-1102 ...
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R254 SPH Figure 56. Stack Pointer High (FEh: Read/Write) R255 SPL Figure 57. Stack Pointer Low (FFh: Read/Write) PS019401-1102 ...
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Package Information Package information is shown in Figure 58, Figure 59, Figure 60, and Figure 61. Figure 58. 40-Pin DIP Package Diagram Figure 59. 44-Pin PLCC Package Diagram PS019401-1102 40/44/48-Pin Low-Voltage IR OTP ...
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Figure 60. 44-Pin QFP Package Design PS019401-1102 40/44/48-Pin Low-Voltage IR OTP Z86D73 ...
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... Detail A Figure 61. 48-Pin SSOP Package Design Note: Please check with ZiLOG on the actual bonding diagram and coordinate for chip-on-board assembly. PS019401-1102 Detail SEATING PLANE L 0-8˚ Z86D73 40/44/48-Pin Low-Voltage IR OTP CONTROLLING DIMENSIONS : MM LEADS ARE COPLANAR WITHIN .004 INCH ...
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... Table 20. Z86D73 Ordering Information 8.0 MHz 40-Pin DIP 8.0 MHz 44-Pin PLCC Z86D7308PSC Z86D7308VSC Die Form Please contact ZiLOG. For fast results, contact your local ZiLOG sales office for assistance in ordering the part desired. Codes Package P = Plastic DIP F = Plastic Quad Flat Pack H = SSOP ...
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... The document states what ZiLOG knows about this product at this time, but additional features or nonconfor- mance with some aspects of the document might be found, either by ZiLOG or its customers in the course of further application and characterization work. In addi- tion, ZiLOG cautions that delivery might be uncertain at times, due to start-up yield issues ...