Z8F042AHJ020SC00TR Zilog, Z8F042AHJ020SC00TR Datasheet - Page 10

• Manufacturer Part Number: Z8F042AHJ020SC00TR
• Description: IC ENCORE XP MCU FLASH 4K 28SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F042AHJ020SC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 23
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Z8F042AHJ020SC00T

Table 5. Z8 Encore! XP
UP006912-0308
Sl
No. Summary
6
7
8
9
10
11
12
PD0 will not output a
strong high.
VBO/POR
Hysteresis is greater
than specified in the
product
specification.
ADC differential
mode calibration
data.
WDT Default
Timeout Period
longer than
specified.
IPO current
consumption higher
than typically
specified.
Open Drain Output
Control only on Port
A.
ADC Internal
Reference Voltage
Error.
0352 and Before 0426 (Continued)
®
Description
The PMOS output device of the PD0 port is disabled. The PD0 port will not
output a high level unless the internal pull-up resistor is enabled. This pull-up
resistor is enabled by default but it should not be turned off unless the port is
pulled up externally. Because there is no active drive high, the PD0 port will
only produce slow rising edges.
Workaround
If a fast rising edge response time is required, use another GPIO port.
The hysteresis has been measured to be around 100 mV.
Workaround
None.
The ADC calibration data stored in the info block will cause significant error for
negative input values on the ADC. This is a production test/calibration issue.
Workaround
Manually re-calibrate the device for negative ADC input values.
In the product specification the default timeout period is 100 ms. However, for
this version of silicon, the default is equal to the maximum timeout value.
Workaround
Manually set the WDT timeout to the desired value.
When the IPO is enabled, the product specification gives a typical current con-
sumption of 300 µA. The consumption for these date codes is typically 1.5 mA.
Workaround
None.
Open drain output configuration set by Port A-D Output Control sub registers
is possible only for Port A pins. It is not possible to configure Port B, C, D pins
for open drain output.
Workaround
None. Use Port A pins for open drain output.
Internal Reference Voltage (Vref) set by REFSEL field in the ADC Control
Register was not set optimally, reporting 1.91 V for a specified 2.0 V setting.
Workaround
None. External Vref sourced ADC measurements are not affected by this
errata.
F082A Series Errata (20- and 28-pin) Devices with Date Codes
Errata for Z8 Encore! XP
®
F082A Series
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