M37516F8HP Renesas Electronics America, M37516F8HP Datasheet - Page 32

• Manufacturer Part Number: M37516F8HP
• Description: IC 740 MCU FLASH 32K 48QFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37516F8HP

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

7516 Group
[I
The I
register to store receive data and write transmit data.
When transmit data is written into this register, it is transferred to
the outside from bit 7 in synchronization with the SCL clock, and
each time one-bit data is output, the data of this register are
shifted by one bit to the left. When data is received, it is input to
this register from bit 0 in synchronization with the SCL clock, and
each time one-bit data is input, the data of this register are shifted
by one bit to the left. The minimum 2 machine cycles are required
from the rising of the S
The I
I
the I
struction to the I
the MST bit of the I
SCL is output by a write instruction to the I
Reading data from the I
gardless of the ES0 bit value.
[I
The I
slave address and a read/write bit. In the addressing mode, the
slave address written in this register is compared with the address
data to be received immediately after the START condition is de-
tected.
•Bit 0: Read/write bit (RWB)
This is not used in the 7-bit addressing mode. In the 10-bit ad-
dressing mode, the first address data to be received is compared
with the contents (SAD6 to SAD0 + RWB) of the I
ister.
The RWB bit is cleared to “0” automatically when the stop condi-
tion is detected.
•Bits 1 to 7: Slave address (SAD0–SAD6)
These bits store slave addresses. Regardless of the 7-bit address-
ing mode and the 10-bit addressing mode, the address data
transmitted from the master is compared with the contents of
these bits.
Rev.1.01
2
C-BUS interface enable bit (ES0 bit : bit 3 of address 002E
2
2
C Data Shift Register (S0)] 002B
C Address Register (S0D)] 002C
2
2
2
C control register is “1”. The bit counter is reset by a write in-
2
C data shift register is in a write enable status only when the
C data shift register (S0 : address 002B
C address register (address 002C
Jul 01, 2003
2
C data shift register. When both the ES0 bit and
2
C status register (address 002D
CL
2
C data shift register is always enabled re-
clock until input to this register.
page 30 of 89
16
2
C data shift register.
) consists of a 7-bit
16
) is an 8-bit shift
16
16
2
C address reg-
16
) are “1,” the
16
) of
Fig. 28 Structure of I
S A D 6 S A D 5 S A D 4 SAD3 S A D 2 SAD1 SAD0 RWB
b7
2
C address register
b 0
I
( S 0 D : a d d r e s s 0 0 2 C
2
R e a d / w r i t e b i t
S l a v e a d d r e s s
C a d d r e s s r e g i s t e r
1 6
)