M37516F8HP Renesas Electronics America, M37516F8HP Datasheet - Page 40

• Manufacturer Part Number: M37516F8HP
• Description: IC 740 MCU FLASH 32K 48QFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37516F8HP

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

7516 Group
Example of Master Transmission
An example of master transmission in the standard clock mode, at
the SCL frequency of 100 kHz and in the ACK return mode is
shown below.
Example of Slave Reception
An example of slave reception in the high-speed clock mode, at
the SCL frequency of 400 kHz, in the ACK non-return mode and
using the addressing format is shown below.
Rev.1.01
register (address 002C
in the I
transmission/reception mode can become initializing condition.
control register (address 002E
register (address 002D
high-order 7 bits of the I
and set “0” in the least significant bit.
ate a START condition. At this time, an SCL for 1 byte and an
ACK clock automatically occur.
Set transmit data in the I
At this time, an SCL and an ACK clock automatically occur.
ate a STOP condition if ACK is not returned from slave
reception side or transmission ends.
When a START condition is received, an address comparison is
• When the transmitted addresses agree with the address set
• In the cases other than the above AD0 and AAS of the I
When receiving control data of more than 1 byte, repeat step
Set a slave address in the high-order 7 bits of the I
Set the ACK return mode and SCL = 100 kHz by setting “85
Set “00
Set a communication enable status by setting “08
Confirm the bus free condition by the BB flag of the I
Set the address data of the destination of transmission in the
Set “F0
When transmitting control data of more than 1 byte, repeat step
Set “D0
Set a slave address in the high-order 7 bits of the I
Set “00
Set a communication enable status by setting “08
•When all transmitted addresses are “0” (general call):
Set dummy data in the I
When a STOP condition is detected, the communication ends.
Set the no ACK clock mode and SCL = 400 kHz by setting
register (address 002C
“25
transmission/reception mode can become initializing condition.
control register (address 002E
performed.
AD0 of the I
and an interrupt request signal occurs.
in
AAS of the I
and an interrupt request signal occurs.
tus register (address 002D
request signal occurs.
.
16
:
” in the I
2
16
C clock control register (address 002F
16
16
16
” in the I
” in the I
” in the I
” in the I
Jul 01, 2003
2
2
2
C status register (address 002D
C status register (address 002D
C clock control register (address 002F
2
2
2
2
C status register (address 002D
C status register (address 002D
C status register (address 002D
C status register (address 002D
16
16
16
2
2
2
) and “0” into the RWB bit.
).
C data shift register (address 002B
C data shift register (address 002B
C data shift register (address 002B
) and “0” in the RWB bit.
page 38 of 89
16
16
16
) are set to “0” and no interrupt
).
).
16
16
16
).
) is set to “1”
) is set to “1”
16
16
16
16
2
2
” in the I
” in the I
16
16
) to gener-
C address
) to gener-
C address
16
2
) so that
) so that
C status
).
2
C sta-
16
16
16
16
2
2
C
C
).
).
”
)
.