M38869FFAHP Renesas Electronics America, M38869FFAHP Datasheet - Page 43

• Manufacturer Part Number: M38869FFAHP
• Description: IC 740 MCU FLASH 61K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38869FFAHP

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 64
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

MULTI-MASTER I
The multi-master I
cuit, conforming to the Philips I
interface, offering both arbitration lost detection and a synchro-
n o u s f u n c t i o n s , i s u s e f u l f o r t h e m u l t i - m a s t e r s e r i a l
communications.
Figure 35 shows a block diagram of the multi-master I
terface and Table 9 lists the multi-master I
functions.
This multi-master I
register, the I
the I
condition control register and other control circuits.
When using the multi-master I
more to .
Fig. 35 Block diagram of multi-master I
40
: Purchase of MITSUBISHI ELECTRIC CORPORATIONS I
an I
2
C control register, the I
2
C system, provided that the system conforms to the I
S 2 D
S T S P
S E L
S e r i a l d a t a
( S
S e r i a l
c l o c k
( S
D A
S I S
C L
2
)
I
C data shift register, the I
2
)
C s t a r t / s t o p c o n d i t i o n
S I P
2
C-BUS interface is a serial communications cir-
2
c o n t r o l r e g i s t e r
S S C 4 S S C 3 S S C 2 S S C 1 S S C 0
C-BUS interface consists of the I
N o i s e
e l i m i n a t i o n
c i r c u i t
N o i s e
e l i m i n a t i o n
c i r c u i t
I n t e r r u p t
g e n e r a t i n g
c i r c u i t
2
C-BUS INTERFACE
2
C status register, the I
2
2
C-BUS data transfer format. This
C-BUS interface, set 1 MHz or
I n t e r r u p t r e q u e s t s i g n a l
( S
C L
C l o c k
c o n t r o l
c i r c u i t
2
S
C clock control register,
D A
2
C-BUS interface
I R Q )
D a t a
c o n t r o l
c i r c u i t
c i r c u i t
c i r c u i t
2
B B
C-BUS interface
A L
2
S 0 D
I
2
2
C start/stop
2
2
C Standard Specification as defined by Philips.
2
C components conveys a license under the Philips I
C c l o c k c o n t r o l r e g i s t e r
b 7
C address
C-BUS in-
S A D 6 S A D 5 S A D 4 S A D 3 S A D 2 S A D 1 S A D 0 R B W
A C K
S 2
b 7
S
b 7
0
A C K
B I T
A d d r e s s c o m p a r a t o r
I
I
2
2
M O D E
F A S T
C d a t a s h i f t r e g i s t e r
C a d d r e s s r e g i s t e r
C C R 4 C C R 3 C C R 2 C C R 1 C C R 0
Table 9 Multi-master I
C l o c k d i v i s i o n
System clock
Communication mode
S
CL
clock frequency
Format
Item
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b 0
b 0
S t o p s e l e c t i o n
b 0
= f(X
= f(X
I n t e r n a l d a t a b u s
MITSUBISHI MICROCOMPUTERS
IN
IN
2
C-BUS interface functions
)/2 (high-speed mode)
)/8 (middle-speed mode)
In conformity with Philips I
standard:
In conformity with Philips I
standard:
16.1 kHz to 400 kHz (at = 4 MHz)
20.2 kHz to 312.5 kHz (at
M S T T R X B B P I N
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
Master transmission
Master reception
Slave transmission
Slave reception
b 7
S 1
b 7
T I S S
S y s t e m c l o c k ( )
2
C Patent Rights to use these components
C L K
S T P
I n t e r r u p t
g e n e r a t i n g
c i r c u i t
1 0 B I T
S A D
I
2
A L S
C c l o c k c o n t r o l r e g i s t e r
Function
3886 Group
E S 0
A L A A S A D 0 L R B
I
2
C s t a t u s r e g i s t e r
I n t e r r u p t r e q u e s t s i g n a l
( I
2
B C 2 B C 1 B C 0
S 1 D
C I R Q )
B i t c o u n t e r
2
2
C-BUS
C-BUS
= 5 MHz)
b 0
b 0