C8051F064 Silicon Laboratories Inc, C8051F064 Datasheet - Page 219

• Manufacturer Part Number: C8051F064
• Description: IC 8051 MCU 64K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F06xr

Specifications of C8051F064

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

18.2. Ports 4 through 7 (C8051F060/2/4/6 only)
All Port pins on Ports 4 through 7 can be accessed as General-Purpose I/O (GPIO) pins by reading and
writing the associated Port Data registers (See Figure 18.19, Figure 18.21, Figure 18.23, and
Figure 18.25), a set of SFRs which are byte-addressable. Note that Port 4 has only three pins: P4.5, P4.6,
and P4.7. Note also that the Port 4, 5, 6, and 7 registers are located on SFR Page F. The SFRPAGE reg-
ister must be set to 0x0F to access these Port registers.
A Read of a Port Data register (or Port bit) will always return the logic state present at the pin itself, regard-
less of whether the Crossbar has allocated the pin for peripheral use or not. An exception to this occurs
during the execution of a read-modify-write instruction (ANL, ORL, XRL, CPL, INC, DEC, DJNZ, JBC,
CLR, SETB, and the bitwise MOV write operation). During the read cycle of the read-modify-write instruc-
tion, it is the contents of the Port Data register, not the state of the Port pins themselves, which is read.
18.2.1. Configuring Ports which are not Pinned Out
Although P3, P4, P5, P6, and P7 are not brought out to pins on the C8051F061/3/5/7 devices, the Port
Data registers are still present and can be used by software. Because the digital input paths also remain
active, it is recommended that these pins not be left in a ‘floating’ state in order to avoid unnecessary
power dissipation arising from the inputs floating to non-valid logic levels. This condition can be prevented
by any of the following:
18.2.2. Configuring the Output Modes of the Port Pins
The output mode of each port pin can be configured to be either Open-Drain or Push-Pull. In the Push-Pull
configuration, a logic 0 in the associated bit in the Port Data register will cause the Port pin to be driven to
GND, and a logic 1 will cause the Port pin to be driven to VDD. In the Open-Drain configuration, a logic 0 in
the associated bit in the Port Data register will cause the Port pin to be driven to GND, and a logic 1 will
cause the Port pin to assume a high-impedance state. The Open-Drain configuration is useful to prevent
contention between devices in systems where the Port pin participates in a shared interconnection in
which multiple outputs are connected to the same physical wire.
The output modes of the Port pins on Ports 4 through 7 are determined by the bits in their respective
PnMDOUT Output Mode Registers. Each bit in PnMDOUT controls the output mode of its corresponding
port pin (see Figure 18.20, Figure 18.22, Figure 18.24, and Figure 18.26). For example, to place Port pin
5.3 in push-pull mode (digital output), set P5MDOUT.3 to logic 1. All port pins default to open-drain mode
upon device reset.
18.2.3. Configuring Port Pins as Digital Inputs
A Port pin is configured as a digital input by setting its output mode to “Open-Drain” and writing a logic 1 to
the associated bit in the Port Data register. For example, P7.7 is configured as a digital input by setting
P7MDOUT.7 to a logic 0 and P7.7 to a logic 1.
18.2.4. Weak Pull-ups
By default, each Port pin has an internal weak pull-up device enabled which provides a resistive connec-
tion (about 100 k) between the pin and VDD. The weak pull-up devices can be globally disabled by writ-
1. Leave the weak pull-up devices enabled by setting WEAKPUD (XBR2.7) to a logic 0.
2. Configure the output modes of P3, P4, P5, P6, and P7 to “Push-Pull” by writing 0xFF to the
3. Force the output states of P3, P4, P5, P6, and P7 to logic 0 by writing zeros to the Port Data
associated output mode register (PnMDOUT).
registers: P3 = 0x00, P4 = 0x00, P5 = 0x00, P6= 0x00, and P7 = 0x00.
Rev. 1.2
C8051F060/1/2/3/4/5/6/7
219