DS87C550-QNL Maxim Integrated Products, DS87C550-QNL Datasheet
DS87C550-QNL
Specifications of DS87C550-QNL
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DS87C550-QNL Summary of contents
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... Available in 68-Pin PLCC, 80-Pin PQFP, and 68-Pin Windowed CLCC The High-Speed Microcontroller User’s Guide and High-Speed Microcontroller User’s Guide: DS87C550 Supplement must be used in conjunction with this data sheet. Download them at www.maxim-ic.com/user_guides. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels ...
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... A/D capability should read Application Note 2: The DS87C550 as an Upgrade for 8051 Derivatives. ORDERING INFORMATION MAX CLOCK PART SPEED (MHz) DS87C550-QCL 33 DS87C550-QCL+ 33 DS87C550-FCL 33 DS87C550-FCL+ 33 DS87C550-QNL 33 DS87C550-QNL+ 33 DS87C550-FNL 33 DS87C550-FNL+ 33 DS87C550-KCL Denotes a Pb-free/RoHS-compliant device. The windowed ceramic LCC package is intrinsically Pb free. * TEMP RANGE PIN-PACKAGE 0°C to +70°C 68 PLCC 0° ...
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... DS87C550 BLOCK DIAGRAM Figure ...
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... Input is possible since any external circuit whose output drives the port will overcome the weak pullup. When software writes any Port 1 pin, the DS87C550 will activate a strong pulldown that remains on until either written or a reset occurs. Writing a 1 after the port has been at 0 will cause a strong transition driver to turn on, followed by a weaker sustaining pullup ...
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PLCC/ QFP SIGNAL NAME CLCC 50-57 51- P0.0 (AD0 P0.1 (AD1 P0.2 (AD2 P0.3 (AD3 P0.4 (AD4 P0.5 (AD5 P0.6 (AD6 P0.7 (AD7) 38-42 ...
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PLCC/ QFP SIGNAL NAME CLCC 1, 64-71 P5.0-P5.7 62- 3-6, 32 28, 29 P6.0-P6.5 33 P6.7 74- ...
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... Thus the fastest instruction, 1 machine cycle, executes three times faster for the same crystal frequency. Note that these are identical instructions. The majority of instructions on the DS87C550 will see the full speed improvement. However, some instructions will achieve between 1.5 and 2 improvement. Regardless of specific performance improvements, all instructions are faster than the original 8051 ...
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... Therefore, they required the same amount of time. In the DS87C550, the MOVX instruction takes as little as two machine cycles or eight oscillator cycles, but the “MOV direct, direct” uses three machine cycles or 12 oscillator cycles. While both are faster than their original counterparts, they now have different execution times ...
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SPECIAL FUNCTION REGISTER LOCATION: Table 2 continued REGISTER BIT7 BIT6 ADCON2 OUTCF MUX2 ADMSB ADLSB WINHI WINLO IP - PAD SADEN0 SADEN1 T2CON TF2 EXF2 T2MOD - - PORT4 CMT1 CMT0 - - ROMSIZE PORT5 ADC7 ADC6 STATUS PIP HIP ...
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... As is convention within the 8051 architecture, the DS87C550 uses three memory areas. The total memory configuration of the DS87C550 is 8kB of EPROM, 1kB of data SRAM and 256 bytes of scratchpad or direct RAM. The 1kB of data space SRAM is read/write accessible and is memory mapped. This on-chip SRAM is reached by the MOVX instruction ...
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... When disabled, the 1kB memory area is transparent to the system memory map. Any MOVX directed to the space between 0000h and FFFFh goes to the expanded bus on Ports 0 & 2. This also is the default condition. This default allows the DS87C550 to drop into an existing system that uses these addresses for other hardware and still have full compatibility. ...
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... In older members of the family, there is no further change in setup and hold times regardless of the number of stretch cycles selected. In the DS87C550 however, when a stretch value above is selected, the timing of the interface changes dramatically to allow for very slow peripherals. First, the ALE signal is increased by 1 machine cycle ...
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... INC instruction. Each INC DPS Instruction will toggle the active data pointer. Unlike the standard 8051, the DS87C550 has the ability to decrement as well as increment the data pointers without additional instructions. When the INC DPTR instruction is executed, the active DPTR is incremented or decremented according to the ID1, ID0 (DPS ...
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... The four phases of a single instruction execution clock are also called a single machine cycle clock. Instructions in the DS87C550 all use the machine cycle as the fundamental unit of measure and are executed in from one to five of these machine ...
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... It is important to note that the clock multiplier function does not increase the maximum clock (system clock) rate of the device. The DS87C550 operates at a maximum system clock rate of 33MHz. Therefore, the maximum crystal frequency is 8.25MHz when a clock multiplier used, and is 16.5MHz when a clock multiplier used ...
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... OSCILLATOR-FAIL DETECT The DS87C550 contains a unique safety mechanism called an on-chip Oscillator-Fail Detect circuit. When enabled, this circuit causes the processor to be reset if the oscillator frequency falls below 40kHz. The processor is held in reset until the oscillator frequency rises above 40kHz. In operation, this circuit can provide a backup for the watchdog timer ...
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... Power Management Mode offers a complete scheme of reduced internal clock speeds that allow the CPU to run software but to use substantially less power. Normally, during default operation, the DS87C550 uses 4 clocks per machine cycle. Thus the instruction cycle (machine cycle clock) rate is clock/4. At 33MHz crystal speed, the instruction cycle speed is 8 ...
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... Switchback One of the other unique features included on the DS87C550 is Switchback. Simply, Switchback when enabled will allow serial ports and interrupts to automatically switch back from divide-by-1024 (PMM) to divide-by-4 (standard speed operation). This feature makes it very convenient to use the Power Management Mode in real time applications. Of course to return to a divide-by-4 clock rate from divide- by-1024 PMM, software can simply select the CD1 & ...
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... BAND-GAP SELECT The DS87C550 provides two enhancements to the Stop mode. As described below, the DS87C550 provides a band-gap reference to determine Power-fail Interrupt and Reset thresholds. The default state is that the band-gap reference is off while in Stop mode. This mode allows the extremely low-power state mentioned above ...
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... Entering Stop mode turns off the crystal oscillator and all internal clocks to save power. When exiting Stop mode, the external crystal may require begin oscillating again. The DS87C550 can eliminate that delay through the use of the internal ring oscillator, resuming operation in less than 100 ns when exiting Stop mode ...
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... EMI REDUCTION One of the major contributors to radiated noise in an 8051-based system is the toggling of ALE. The DS87C550 allows software to disable ALE when not used by setting the ALEOFF (PMR.2) bit When ALEOFF = 1, ALE will still toggle during an off-chip MOVX. However, ALE will remain inactive when performing on-chip memory access ...
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Selecting a single analog signal for conversion is achieved by software writing the desired channel number (0 through 7) into the MUX2 -MUX0 bits (ADCON2.6-4). The selected input is then provided to a sample and hold circuit that maintains a ...
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... A “1111111111” will be output for voltages from (A The DS87C550 offers a unique feature that allows the result of an A/D conversion to be compared with two user-defined values stored in the WINHI and WINLO registers. The results of this comparison will set or clear the WCM (ADCON 1 ...
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... PULSE WIDTH MODULATION The DS87C550 contains four independent 8-bit pulse width modulator (PWMs) functions each with independently selectable clock sources. For more precise modulation operations, two 8-bit PWM functions (PWM0 & PWM1 and/or PWM2 & PWM3) can be cascaded together to form a 16-bit PWM function ...
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Each clock generator has an associated SFR that contains the 8-bit reload value. These registers are called PW0FG, PW1FG, PW2FG, and PW3FG (see SFR map for addresses). In addition, there is a frequency generator enable bit (PW0EN, PW1EN, PW2EN, & ...
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... GENERAL PURPOSE TIMERS/COUNTERS The DS87C550 contains three general-purpose timer/ counters. Timers 0 and 1 are standard 8051 16-bit timer/counters with three modes of operation. Each of these devices can be used as a 13-bit timer/counter, 16-bit timer/counter or 8-bit timer/counter with auto-reload ...
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To enable the interrupt, the Timer 2 interrupt enable bit ET2 (EIE.7) must be set The 8- bit overflow interrupt or the 16-bit overflow interrupt is then individually enabled by setting TF2BS (T2SEL.6) or TF2S (T2SEL.7). ...
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SETR REGISTER FUNCTIONALITY SETR.7 TGFF1 SETR.6 TGFF0 SETR.5 CMS5 SETR.4 CMS4 SETR.3 CMS3 SETR.2 CMS2 SETR.1 CMS1 SETR.0 CMS0 RSTR.7 CMTE1 RSTR.6 CMTE0 RSTR.5 CMR5 RSTR.4 CMR4 RSTR.3 CMR3 RSTR.2 CMR2 RSTR.1 CMR1 RSTR.0 CMR0 WATCHDOG TIMER The free-running watchdog ...
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... Software can determine that a Power-On Reset has occurred by checking the Power-On Reset flag (POR=WDCON.6). Software should clear the POR bit after reading it. The Reset pin of the DS87C550 is both an input and an output. When the processor is being held in reset by the power-fail detection circuitry, the reset pin will be actively pulled high by the processor, and can therefore be used as an input to other external devices ...
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... External interrupts 2/3/4/5 also require the appropriate bits in the CTCON register to be configured before the interrupt is fully enabled. EPROM PROGRAMMING The DS87C550 follows 8kB EPROM standards for the 8051 family available erasable, ceramic windowed package and in plastic packages for one-time user-programmable versions. The part has unique signature information so programmers can support its specific EPROM options. ...
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... SECURITY OPTIONS The DS87C550 employs a standard three-level lock that restricts viewing of the EPROM contents. A 64- byte Encryption Array allows the authorized user to verify memory by presenting the data in encrypted form. Lock Bits The security lock consists of 3 lock bits. These bits select a total of four levels. Higher levels provide increasing security but also limit application flexibility ...
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... FFh. Simply programming the array to a non-FFh state will cause the encryption to function. EPROM ERASURE CHARACTERISTICS Erasure of the information stored in the DS87C550’s EPROM occurs when the isolated gate structure of the EPROM stage element is exposed to certain wavelengths of light. While the gate structure is to some degree sensitive to a wide range of wavelengths mostly wavelengths shorter than approximately 4,000 angstroms that are most effective in erasing the EPROM ...
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... OTHER EPROM OPTIONS The DS87C550 has user-selectable options that must be set before beginning software execution. These options use EPROM bits rather than SFRs. The EPROM selectable options may be programmed as shown in Table 10. The Option Register sets or reads these selections. The bits in the Option Register have the following function: Bit 7 -4 Reserved ...
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ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground………………………………………-0. Voltage Range on V Relative to Ground…………………………………………………..-0.3V to 6.0V CC Operating Temperature Range……………………………………………………………..-40°C to +85°C Storage Temperature Range………………………………………………………………-55°C to +125°C Soldering Temperature………………………………………………………...See IPC/JEDEC J-STD-020 Stresses ...
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... NOTES FOR DS87C550 DC ELECTRICAL CHARACTERISTICS: All parameters apply to both commercial and industrial temperature operation unless otherwise noted. These parameters are guaranteed by design. 1. Voltage referenced to digital ground (GND). 2. Active current measured with 33MHz clock source on XTAL1, V disconnected. 3. Idle mode current measured with 33MHz clock source on XTAL1, V pins disconnected ...
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A/D CONVERTER ELECTRICAL CHARACTERISTICS (AV =V =5V, V =5V REF values are at T =25°C) A PARAMETER Analog Supply Voltage Analog Supply Current Analog Idle Mode Current Analog Power-Down Mode Current Analog Input Voltage External Analog Reference ...
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AC ELECTRICAL CHARACTERISTICS PARAMETER Oscillator Freq. (Ext. Osc.) (Ext. Crystal) ALE Pulse Width Port 0 Address Valid to ALE Low Address Hold after ALE Low ALE Low to Valid Instruction In ALE Low to PSEN Low PSEN Pulse Width PSEN ...
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MOVX CHARACTERISTICS PARAMETER SYMBOL Data Access ALE Pulse t LHLL2 Width Port 0 Address Valid to t AVLL2 ALE Low Address Hold after ALE Low for MOVX t LLAX2 Write t RD Pulse Width RLRH t WR Pulse Width WLWH ...
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TIME PERIODS MCS System Clock Selection 4X/ , CD1, CD0 = 100 2X 4X/ , CD1, CD0 = 000 2X 4X/ , CD1, CD0 = x10 2X 4X/ , CD1, CD0 = x11 2X , PULSE WIDTH WITH STRETCH ...
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EXPLANATION OF AC SYMBOLS In an effort to remain compatible with the original 8051 family, this device specifies the same parameters as such devices, using the same symbols. The following is an explanation of the symbols. t Time A Address ...
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EXTERNAL PROGRAM MEMORY READ CYCLE EXTERNAL DATA MEMORY READ CYCLE ...
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EXTERNAL DATA MEMORY WRITE CYCLE DATA MEMORY WRITE WITH STRETCH ...
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DATA MEMORY WRITE WITH STRETCH=2 DATA MEMORY WRITE WITH STRETCH=4 EXTERNAL CLOCK DRIVE ...
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SERIAL PORT MODE 0 TIMING SERIAL PORT 0 (SYNCHRONOUS MODE) HIGH SPEED OPERATION SM2=1=>TXD CLOCK=XTAL/4 SERIAL PORT 0 (SYNCHRONOUS MODE) SM2=0=>TXD CLOCK=XTAL/ ...
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POWER CYCLE TIMING EPROM PROGRAMMING AND VERIFICATION WAVEFORMS ...
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QUAD FLAT PACK (14 20.0 MM) DIM MIN 0.25 A2 2.55 B 0.30 C 0.13 D 23.70 D1 19.90 E 17.70 E1 13.90 e 0.80 BSC L 0.65 NOTES: 1. DIMENSIONS D1 AND E1 ...
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WINDOWED CLCC LTR MIN A .160 A1 .034 B .026 B1 .017 c .005 CH1 .035 D .978 D1 .940 D2 .910 E .978 E1 .940 E2 .910 e1 .050 BSC MAX .190 - .032 .023 .010 .045 .998 ...
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PLCC NOTE: 1. PIN-1 IDENTIFIER TO BE LOCATED IN ZONE INDICATED. 2. DIMENSIONS ARE IN INCH UNITS. DIM MIN A .165 A1 .090 A2 .020 b .026 b1 .013 c .0075 CH1 .042 D .985 D1 .950 D2 .882 ...
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... REVISION HISTORY The following represent the key differences between the 10/26/04 and 07/05/05 version of the DS87C550 data sheet. Please review this summary carefully. 1. Added Pb-free part numbers to the Ordering Information table. The following represent the key differences between the 06/14/99 and the 10/26/04 version of the DS87C550 data sheet ...