SAK-XC164CM-8F40F AA Infineon Technologies, SAK-XC164CM-8F40F AA Datasheet - Page 43

• Manufacturer Part Number: SAK-XC164CM-8F40F AA
• Description: IC MCU 16BIT 64KB FLSH TQFP-64-8
• Manufacturer: Infineon Technologies
• Series: XC16xr

Specifications of SAK-XC164CM-8F40F AA

• Core Processor: C166SV2
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SPI, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.7 V
• Data Converters: A/D 14x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LFQFP
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: 2xASC, 2xSSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 9
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 14 Channel
• Packages: PG-LQFP-64
• Max Clock Frequency: 40.0 MHz
• Sram (incl. Cache): 6.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 14
• Program Memory: 64.0 KByte
• For Use With: B158-H8961-X-X-7600IN - KIT EASY XC164CMXC164CMUCANIN - KIT U-CAN STARTER XC164CMMCBX167-NET - BOARD EVAL INFINEON CAN/ETHRNTMCBXC167-BASIC - BOARD EVAL BASIC INFINEON XC16X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: SAK-XC164CM-8F40FAACT; SAK-XC164CM-8F40FAACT; SAK-XC164CM-8F40FAAINCT

XC164CM
Derivatives
Functional Description
3.14
Watchdog Timer
The Watchdog Timer represents one of the fail-safe mechanisms which have been
implemented to prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after a reset of the chip, and can be disabled
until the EINIT instruction has been executed (compatible mode), or it can be disabled
and enabled at any time by executing instructions DISWDT and ENWDT (enhanced
mode). Thus, the chip’s start-up procedure is always monitored. The software has to be
designed to restart the Watchdog Timer before it overflows. If, due to hardware or
software related failures, the software fails to do so, the Watchdog Timer overflows and
generates an internal hardware reset.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by
2/4/128/256. The high byte of the Watchdog Timer register can be set to a prespecified
reload value (stored in WDTREL) in order to allow further variation of the monitored time
interval. Each time it is serviced by the application software, the high byte of the
Watchdog Timer is reloaded and the low byte is cleared. Thus, time intervals between
13 μs and 419 ms can be monitored (@ 40 MHz).
The default Watchdog Timer interval after reset is 3.28 ms (@ 40 MHz).
Data Sheet
41
V1.4, 2007-03