LT1055CN8 Linear Technology, LT1055CN8 Datasheet - Page 9

• Manufacturer Part Number: LT1055CN8
• Description: IC PREC OP-AMP JFET HI-SPD 8-DIP
• Manufacturer: Linear Technology

Specifications of LT1055CN8

• Amplifier Type: J-FET
• Number Of Circuits: 1
• Slew Rate: 12 V/µs
• Gain Bandwidth Product: 4.5MHz
• Current - Input Bias: 30pA
• Voltage - Input Offset: 120µV
• Current - Supply: 2.8mA
• Voltage - Supply, Single/dual (±): ±5 V ~ 18 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Output Type: -
• Current - Output / Channel: -
• -3db Bandwidth: -

APPLICATIONS
Teflon is a trademark of Dupont.
The LT1055/LT1056 may be inserted directly into LF155A/
LT355A, LF156A/LT356A, OP-15 and OP-16 sockets. Off-
set nulling will be compatible with these devices with the
wiper of the potentiometer tied to the positive supply.
No appreciable change in offset voltage drift with tempera-
ture will occur when the device is nulled with a potentiom-
eter, R
The LT1055/LT1056 can also be used in LF351, LF411,
AD547, AD611, OPA-111, and TL081 sockets, provided
that the nulling cicuitry is removed. Because of the LT1055/
LT1056’s low offset voltage, nulling will not be necessary
in most applications.
Achieving Picoampere/Microvolt Performance
In order to realize the picoampere-microvolt level accu-
racy of the LT1055/LT1056 proper care must be exer-
cised. For example, leakage currents in circuitry external
to the op amp can significantly degrade performance. High
quality insulation should be used (e.g. Teflon™, Kel-F);
cleaning of all insulating surfaces to remove fluxes and
other residues will probably be required. Surface coating
may be necessary to provide a moisture barrier in high
humidity environments.
Board leakage can be minimized by encircling the input
circuitry with a guard ring operated at a potential close to
that of the inputs: in inverting configurations the guard
ring should be tied to ground, in noninverting connnections
to the inverting input at pin 2. Guarding both sides of the
printed circuit board is required. Bulk leakage reduction
depends on the guard ring width.
P
, ranging from 10k to 200k.
U
2
3
–
+
1
Offset Nulling
LT1055
LT1056
R
INFORMATION
V
P
U
–
5
4
7
6
LT1055/56 AI1
V
W
OUT
+
U
The LT1055/LT1056 has the lowest offset voltage of any
JFET input op amp available today. However, the offset
voltage and its drift with time and temperature are still not
as good as on the best bipolar amplifiers because the
transconductance of FETs is considerably lower than that
of bipolar transistors. Conversely, this lower transcon-
ductance is the main cause of the significantly faster
speed performance of FET input op amps.
Offset voltage also changes somewhat with temperature
cycling. The AM grades show a typical 20µV hysteresis
(30µV on the M grades) when cycled over the –55°C to
125°C temperature range. Temperature cycling from 0°C
to 70°C has a negligible (less than 10µV) hysteresis
effect.
The offset voltage and drift performance are also affected
by packaging. In the plastic N8 package the molding
compound is in direct contact with the chip, exerting
pressure on the surface. While NPN input transistors are
largely unaffected by this pressure, JFET device matching
and drift are degraded. Consequently, for best DC perfor-
mance, as shown in the typical performance distribution
plots, the TO-5 H package is recommended.
Noise Performance
The current noise of the LT1055/LT1056 is practically
immeasurable at 1.8fA/√Hz. At 25°C it is negligible up to
1G of source resistance, R
R
S
). Even at 125°C it is negligible to 100M of R
OFFSET
OUTPUT
TRIM
V
V
–
+
5
6
4
7
GUARD
N/C
8
S
(compound to the noise of
3
LT1055/LT1056
1
2
OFFSET
TRIM
LT1055/56 AI2
S
.
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