CLC414AJE National Semiconductor, CLC414AJE Datasheet - Page 8

• Manufacturer Part Number: CLC414AJE
• Description: IC OP AMP MONO QUAD LP 14-SOIC
• Manufacturer: National Semiconductor

Specifications of CLC414AJE

• Amplifier Type: Current Feedback
• Number Of Circuits: 4
• Slew Rate: 1000 V/µs
• -3db Bandwidth: 90MHz
• Current - Input Bias: 2µA
• Voltage - Input Offset: 2000µV
• Current - Supply: 10mA
• Current - Output / Channel: 70mA
• Voltage - Supply, Single/dual (±): 5 V ~ 12 V, ±2.5 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Output Type: -
• Gain Bandwidth Product: -
• Other names: *CLC414AJE

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magnitude of this undesirable effect. This effect is measured
by driving one or more channels and observing the output of
the other undriven channel(s). The CLC414 plot page offers
two different graphs detailing the effect of crosstalk over
frequency. One plot entitled “All-Hostile Crosstalk Isolation”
graphs
crosstalk refers to the condition where three channels are
driven simultaneously while observing the output of the un-
driven fourth channel. Input-referred implies that crosstalk is
directly affected by gain and therefore a higher gain in-
creases the crosstalk effect by a factor equal to that gain
setting.
Channel-to-Channel Pulse Coupling” describes the effect of
crosstalk when one channel is driven with a 2V
the output of the most effected channel is observed.
Printed Circuit Layout
As with any high speed component, a careful attention to the
board layout is necessary for optimum performance. Of par-
all-hostile
The
plot
input-referred
entitled
(Continued)
crosstalk.
“Most
PP
Susceptible
pulse while
All-hostile
8
ticular importance is the careful control of parasitic capaci-
tances on the output pin. As the output impedance plot
shows, the closed loop output for the CLC414 eventually
becomes inductive as the loop gain rolls off with increasing
frequency. Direct capacitive loading on the output pin can
quickly lead to peaking in the frequency response, overshoot
in the pulse response, ringing or even sustained oscillations.
The “Settling Time vs. Capacitive Load” plot should be used
as a starting point for the selection of a series output resistor
when a capacitive load must be driven. A quad amplifier will
require careful attention to signal routing in order to minimize
the effects of crosstalk. Signal coupling through the power
supplies can be reduced with bypass capacitors placed
close to the device supply pins.
Evaluation Board
Evaluation PC boards (part number 730024 for through-hole
and 730031 for SOIC) for the CLC414 are available.