ADM1064ASUZ Analog Devices Inc, ADM1064ASUZ Datasheet - Page 27

• Manufacturer Part Number: ADM1064ASUZ
• Description: IC SEQUENCER/SUPERVISOR 48-TQFP
• Manufacturer: Analog Devices Inc
• Type: Sequencerr

Specifications of ADM1064ASUZ

• Number Of Voltages Monitored: 10
• Output: Programmable
• Voltage - Threshold: Adjustable/Selectable
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• No. Of Supervisors / Monitors: 10
• Supply Voltage Range: 3V To 14.4V
• Supply Current: 4.2mA
• Digital Ic Case Style: TQFP
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADM1064LFEBZ - BOARD EVALUATION FOR ADM1064LFEVAL-ADM1064TQEB - BOARD EVALUATION FOR ADM1064TQ
• Reset: -
• Reset Timeout: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

•
•
Block Write
In a block write operation, the master device writes a block of
data to a slave device. The start address for a block write must
have been set previously. In the ADM1064, a send byte opera-
tion sets a RAM address, and a write byte/word operation sets
an EEPROM address, as follows:
1.
2.
3.
4.
5.
6.
S
1
To set up a 2-byte EEPROM address for a subsequent read,
write, block read, block write, or page erase. In this case, the
command byte is the high byte of EEPROM Address 0xF8
to EEPROM Address 0xFB. The only data byte is the low
byte of the EEPROM address, as shown in Figure 37.
Because a page consists of 32 bytes, only the three MSBs of
the address low byte are important for page erasure. The
lower five bits of the EEPROM address low byte specify the
addresses within a page and are ignored during an erase
operation.
To write a single byte of data to the EEPROM. In this case,
the command byte is the high byte of EEPROM Address
0xF8 to EEPROM Address 0xFB. The first data byte is the
low byte of the EEPROM address, and the second data byte
is the actual data, as shown in Figure 38.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by
the write bit (low).
The addressed slave device asserts an ACK on SDA.
The master sends a command code that tells the slave
device to expect a block write. The ADM1064 command
code for a block write is 0xFC (1111 1100).
The slave asserts ACK on SDA.
The master sends a data byte that tells the slave device how
many data bytes are being sent. The SMBus specification
allows a maximum of 32 data bytes in a block write.
ADDRESS
SLAVE
S
1
ADDRESS
2
SLAVE
2
Figure 38. Single Byte Write to the EEPROM
W A
Figure 37. Setting an EEPROM Address
3
W A
(0xF8 TO 0xFB)
3
HIGH BYTE
ADDRESS
EEPROM
(0xF8 TO 0xFB)
HIGH BYTE
ADDRESS
4
EEPROM
4
5
A
(0x00 TO 0xFF)
A
5
LOW BYTE
ADDRESS
EEPROM
(0x00 TO 0xFF)
6
LOW BYTE
ADDRESS
EEPROM
6
A
7
DATA
8
A
7
8
P
A
9
10
P
Rev. C | Page 27 of 32
7.
8.
9.
10. The master asserts a stop condition on SDA to end the
Unlike some EEPROM devices that limit block writes to within
a page boundary, there is no limitation on the start address
when performing a block write to EEPROM, except when
•
•
Note that the ADM1064 features a clock extend function for
writes to EEPROM. Programming an EEPROM byte takes
approximately 250 μs, which limits the SMBus clock for
repeated or block write operations. The ADM1064 pulls SCL
low and extends the clock pulse when it cannot accept any
more data.
READ OPERATIONS
The ADM1064 uses the following SMBus read protocols.
Receive Byte
In a receive byte operation, the master device receives a single
byte from a slave device, as follows:
1.
2.
3.
4.
5.
6.
In the ADM1064, the receive byte protocol is used to read a
single byte of data from a RAM or EEPROM location whose
address has previously been set by a send byte or write
byte/word operation, as shown in Figure 40.
S
1
ADDRESS
SLAVE
The slave asserts an ACK on SDA.
The master sends N data bytes.
The slave asserts an ACK on SDA after each data byte.
transaction.
There must be at least N locations from the start address to
the highest EEPROM address (0xFBFF) to avoid writing to
invalid addresses.
An address crosses a page boundary. In this case, both
pages must be erased before programming.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
read bit (high).
The addressed slave device asserts an ACK on SDA.
The master receives a data byte.
The master asserts a NACK on SDA.
The master asserts a stop condition on SDA, and the
transaction ends.
2
Figure 40. Single Byte Read from the EEPROM or RAM
W A
S
Figure 39. Block Write to the EEPROM or RAM
1
3
COMMAND 0xFC
(BLOCK WRITE)
ADDRESS
SLAVE
2
4
A
5
R
COUNT
BYTE
A
3
6
DATA
A
7
4
DATA
8
1
9
A
A
5
DATA
2
P
6
ADM1064
A
DATA
N
A P
10