LTC1326CMS8-2.5 Linear Technology, LTC1326CMS8-2.5 Datasheet - Page 6

• Manufacturer Part Number: LTC1326CMS8-2.5
• Description: IC PREC TRPL SUPPLY MONITR 8MSOP
• Manufacturer: Linear Technology
• Type: Multi-Voltage Supervisorr

Specifications of LTC1326CMS8-2.5

• Number Of Voltages Monitored: 3
• Output: Open Drain or Open Collector
• Reset: Active High/Active Low
• Reset Timeout: 140 ms Minimum
• Voltage - Threshold: 2.363V, 3.118V, Adj
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LTC1326/LTC1326-2.5
TYPICAL PERFOR A CE CHARACTERISTICS
PIN
V
the IC. Bypass to ground with ≥ 0.1µF ceramic capacitor.
V
drive for the RST output FET when the voltage on V
less than the voltage on V
V
the Applications Information section).
V
gate drive for RST output FET when the voltage on V
is less than the voltage on V
to V
V
used as a logic input with a 1V threshold. If unused, it can
be tied to either V
GND (Pin 4): Ground.
RST (Pin 5): Reset Logic Output. Active high CMOS logic
output, drives high to V
An external pull-down on the RST pin will drive this pin
high.
6
CC3
CC5
CC3
CC25
CCA
220
215
210
205
200
195
190
225
U
CC3
– 60
(Pin 1): 3.3V Sense Input and Power Supply Pin for
(Pin 2) (LTC1326): 5V Sense Input. Used as gate
(see Dual and Single Supply Monitor Operation in
(Pin 3): 1V Sense, High Impedance Input. Can be
Reset Pulse Width
vs Temperature
(Pin 2) (LTC1326-2.5): 2.5V Sense Input. Used as
FUNCTIONS
.
– 40
U
– 20
TEMPERATURE (°C)
0
CC3
20
U
or V
CC3
40
CC5
CC25
, buffered complement of RST.
60
W
CC25
. If unused, it can be tied to
.
1326/2.5 G13
80
. If unused, it can be tied
U
100
110.0
107.5
105.0
112.5
102.5
100.0
97.5
95.0
– 60
“Soft” Reset Pulse Width
vs Temperature
– 40
CC3
– 20
CC3
TEMPERATURE (°C)
is
0
20
RST (Pin 6): Reset Logic Output. Active low, open-drain
logic output with weak pull-up to V
greater than V
when one or more of the supplies are below trip
thresholds and held for 200ms after all supplies become
valid. Also asserted after PBR is held low for more than
2 seconds and for an additional 200ms after PBR is
released.
SRST (Pin 7): Soft Reset. Active low, open-drain logic
output with weak pull-up to V
greater than V
for 100µs after PBR is held low for less than 2 seconds
and released.
PBR (Pin 8): Push-Button Reset. Active low logic input
with weak pull-up to V
V
than 2 seconds, outputs a soft reset 100µs pulse on the
SRST pin. When PBR is asserted for greater than 2
seconds, the RST output is forced low and remains low
until 200ms after PBR is released.
CC3
40
when interfacing to 5V logic. When asserted for less
60
1326/2.5 G14
80
100
CC3
CC3
when interfacing to 5V logic. Asserted
when interfacing to 5V logic. Asserted
1.90
2.25
2.20
2.15
2.10
2.05
2.00
1.95
CC3
– 60
PBR Assertion Time to Reset
vs Temperature
. Can be pulled up greater than
– 40
– 20
CC3
TEMPERATURE (°C)
CC3
. Can be pulled up
0
. Can be pulled up
20
40
60
1326/2.5 G15
80
132625fc
100