LTC1326CMS8-2.5 Linear Technology, LTC1326CMS8-2.5 Datasheet - Page 8

• Manufacturer Part Number: LTC1326CMS8-2.5
• Description: IC PREC TRPL SUPPLY MONITR 8MSOP
• Manufacturer: Linear Technology
• Type: Multi-Voltage Supervisorr

Specifications of LTC1326CMS8-2.5

• Number Of Voltages Monitored: 3
• Output: Open Drain or Open Collector
• Reset: Active High/Active Low
• Reset Timeout: 140 ms Minimum
• Voltage - Threshold: 2.363V, 3.118V, Adj
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
LTC1326/LTC1326-2.5
Operation
The LTC1326/LTC1326-2.5 are micropower, high accu-
racy triple supply monitoring circuits. The parts have two
basic functions: generation of a reset when power sup-
plies are out of range, and generation of reset or a “soft”
reset when the PBR pin is pulled low.
Supply Monitoring
All three V
thresholds for 200ms before the reset output is released.
The parts will assert reset during power-up, power-down
and brownout conditions on any one or more of the V
inputs.
On power-up, either the V
or the V
the drive circuits for the RST pin. This ensures that RST
will be low when V
as any one of the V
threshold, RST will stay a logic low. Once all of the V
inputs rise above their thresholds, an internal timer is
started and RST is released after 200ms. The RST pin
outputs the inverted state of what is seen on RST pin.
RST is reasserted whenever any one of the V
drops below its predetermined threshold and remains
asserted until 200ms after all of the V
their thresholds.
On power-down, once any of the V
its threshold, RST is held at a logic low. A logic low of 0.4V
is guaranteed until V
and V
8
TI I G DIAGRA S
V
W
RST
CCX
CC25
U
CC25
on the LTC1326-2.5 drop below 1V.
V
RTX
CC
or V
inputs must be above predetermined
CC3
CC5
U
CC
V
CC3
pin on the LTC1326-2.5, can power
CC
, V
inputs is below its predetermined
Monitor Timing
and V
CC25
CC5
U
W
or V
or V
CC5
CC3
CC3
on the LTC1326 or V
CC
W
t
pin on the LTC1326,
reaches 1V. As long
RST
CC
inputs drop below
inputs are above
U
CC
1326/2.5 TD01
inputs
CC3
CC
CC
The three internal precision voltage comparators have
response times that are typically 13µs. This slow re-
sponse time helps prevent mistriggering due to tran-
sients on each of the V
suppress transients can be improved by bypassing each
of the V
Push-Button Reset
The parts provide a push-button reset input pin. The PBR
input has an internal pull-up current source to V
PBR pin is not used it can be left floating.
When the PBR is pulled low for less than t
narrow (100µs typ) soft reset pulse is generated on the
SRST output pin after the button is released. The push-
button circuitry contains an internal debounce counter
which delays the output of the soft reset pulse by typically
20ms. This pin can be OR-tied to the RST pin and issue
what is called a “soft” reset. The SRST thereby resets the
microprocessor without interrupting the DRAM refresh
cycle. In this manner DRAM information remains undis-
turbed. Alternatively, SRST may be monitored by the
processor to initiate a software-controlled reset.
When the PBR pin is held low for longer than t
a standard reset is generated on the RST and RST pins.
Once the 2 second period has elapsed, a reset signal is
produced by the push-button logic, thereby clearing the
reset counter. Once the button is released, the reset
counter begins counting the reset period (200ms nomi-
nal). Consequently, the reset outputs remain asserted for
approximately 200ms after the button is released.
SRST
PBR
RST
CC
t < t
inputs with a 0.1µF capacitor to ground.
PB
Push-Button Reset Function Timing
t
DB
t
SRST
CC
t
PB
inputs. The part’s ability to
t
PB
RST
PB
(≈ 2 sec), a
CC3
(≈ 2 sec),
1326/2.5 TD02
. If the
132625fc