LTC695CSW-3.3 Linear Technology, LTC695CSW-3.3 Datasheet - Page 11

• Manufacturer Part Number: LTC695CSW-3.3
• Description: IC MPU SUPRVSRY CIRC 3.3V 16SOIC
• Manufacturer: Linear Technology
• Type: Simple Reset/Power-On Resetr

Specifications of LTC695CSW-3.3

• Number Of Voltages Monitored: 1
• Output: Open Drain or Open Collector
• Reset: Active High/Active Low
• Reset Timeout: 140 ms Minimum
• Voltage - Threshold: 2.9V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: LTC695CS-3.3

APPLICATIONS INFORMATION
If battery connections are made through long wires, a
10Ω to 100Ω series resistor and a 0.1μF capacitor are
recommended to prevent any overshoot beyond V
to the lead inductance (Figure 4).
Table 1 shows the state of each pin during battery back-up.
When the battery switchover section is not used, connect
V
Table 1. Input and Output Status in Battery Back-Up Mode
SIGNAL
V
V
V
BATT ON
PFI
PFO
RESET
RESET
LOW
WDI
WDO
CE IN
CE OUT
OSC IN
OSC SEL
CC
OUT
BATT
BATT
_
LINE Logic low.
to GND and V
STATUS
C2 monitors V
V
The supply current is 1μA maximum.
Logic high. The open-circuit output voltage is equal to V
Power failure input is ignored.
Logic low.
Logic low.
Logic high. The open-circuit output voltage is equal to V
Watchdog input is ignored.
Logic high. The open-circuit output voltage is equal to V
Chip
Logic high. The open-circuit output voltage is equal to V
OSC IN is ignored.
OSC SEL is ignored.
OUT
_
Enable input is ignored.
is connected to V
CE OUT
CE IN
V
CC
V
OUT
OUT
CC
for active switchover.
= V
to V
BATT
BATT
CC
through an internal PMOS switch.
.
Figure 5. Timing Diagram for CE IN and CE OUT
CC
V1
OUT
OUT
OUT
OUT
due
.
.
.
.
V2
Memory Protection
The LTC695-3.3 includes memory protection circuitry
which ensures the integrity of the data in memory by pre-
venting write operations when V
additional pins, CE IN and CE OUT, control the Chip
or Write inputs of CMOS RAM. When V
follows CE IN with a typical propagation delay of 30ns.
When V
CE OUT is forced high, independent of CE IN. CE OUT is
an alternative signal to drive the CE, CS, or Write input of
battery backed up CMOS RAM. CE OUT can also be used
to drive the Store or Write input of an EEPROM, EAROM
or NOVRAM to achieve similar protection. Figure 5 shows
the timing diagram of CE IN and CE OUT.
Figure 4. 10Ω/0.1μF Combination Eliminates Inductive
Overshoot and Prevents Spurious Resets During Battery
Replacement. The 2.7M Pulls the V
While the Battery is Removed, Eliminating Spurious Resets
V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS
CC
LTC694-3.3/LTC695-3.3
falls below the reset voltage threshold or V
10Ω
2.7M
0.1μF
V
CC
OUT
BATT
694/5-3.3 F05
is at invalid level. Two
= V
Pin to Ground
V
BATT
BATT
LTC694-3.3
LTC695-3.3
CC
GND
is 3.3V, CE OUT
694/5-3.3 F04
11
_
Enable
69453fb
BATT
,