LTC695CSW-3.3 Linear Technology, LTC695CSW-3.3 Datasheet - Page 12

• Manufacturer Part Number: LTC695CSW-3.3
• Description: IC MPU SUPRVSRY CIRC 3.3V 16SOIC
• Manufacturer: Linear Technology
• Type: Simple Reset/Power-On Resetr

Specifications of LTC695CSW-3.3

• Number Of Voltages Monitored: 1
• Output: Open Drain or Open Collector
• Reset: Active High/Active Low
• Reset Timeout: 140 ms Minimum
• Voltage - Threshold: 2.9V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: LTC695CS-3.3

APPLICATIONS INFORMATION
LTC694-3.3/LTC695-3.3
12
V
3.3V
3.3V
IN
+
V
0.1μF
0.1μF
≥ 5V
IN
2.4V
2.4V
R1
51k
R2
16k
Figure 6. A Typical Nonvolatile CMOS RAM Application
+
Figure 8. Monitoring Unregulated DC Supply with the
LTC694-3.3/LTC695-3.3’s Power-Fail Comparator
10μF
6.5V
Figure 9. Monitoring Regulated DC Supply with the
LTC694-3.3/LTC695-3.3’s Power-Fail Comparator
Figure 7. Write Protect for RAM with LTC694-3.3
10μF
V
SHDN
LT1129-3.3
OUT SENSE
V
V
V
IN
V
CC
BATT
CC
BATT
LTC695-3.3
GND
LTC694-3.3
V
SHDN
ADJ
LT1129-3.3
OUT SENSE
IN
GND
V
ADJ
OUT
CE OUT
RESET
RESET
RESET
V
CE IN
V
V
OUT
OUT
OUT
+
10μF
+
+
+
30ns PROPAGATION DELAY
FROM DECODER
TO μP
10μF
10μF
200k
R1
27k
R2
16k
R5
5k
100μF
R3
3.3V
2.7M
R3
10k
R4
R4
10k
3.3V
0.1μF
0.1μF
0.1μF
CS
0.1μF
TO μP
TO μP
PFO
PFI
V
CC
PFI
V
PFO
LTC694-3.3
LTC695-3.3
CC
LTC694-3.3
LTC695-3.3
CS
V
CS1
CS2
V
GND
CC
CC
62512
62128
GND
GND
694/5-3.3 F06
RAM
RAM
GND
694/5-3.3 F09
694/5-3.3 F08
694/5-3.3 F07
CE IN can be derived from the microprocessor’s address
decoder output. Figure 6 shows a typical nonvolatile CMOS
RAM application.
Memory protection can also be achieved with the LTC694-
3.3 by using RESET as shown in Figure 7.
Power-Fail Warning
The LTC694-3.3/LTC695-3.3 generate a Power Failure Out-
put (PFO) for early warning of failure in the microprocessor’s
power supply. This is accomplished by comparing the
power failure input (PFI) with an internal 1.3V reference.
PFO goes low when the voltage at the PFI pin is less than
1.3V. Typically PFI is driven by an external voltage divider
(R1 and R2 in Figures 8 and 9) which senses either an
unregulated DC input or a regulated 3.3V output. The
voltage divider ratio can be chosen such that the voltage
at the PFI pin falls below 1.3V several milliseconds before
the 3.3V supply falls below the maximum reset voltage
threshold 3.0V. PFO is normally used to interrupt the
microprocessor to execute shutdown procedure between
PFO and RESET or RESET.
The power-fail comparator, C3, does not have hysteresis.
Hysteresis can be added however, by connecting a resistor
between the PFO output and the noninverting PFI input
pin as shown in Figures 8 and 9. The upper and lower trip
points in the comparator are established as follows:
When PFO output is low, R3 sinks current from the sum-
ming junction at the PFI pin.
When PFO output is high, the series combination of R3
and R4 source current into the PFI summing junction.
V
V
Assuming R4 << R3, V
H
L
=1.3V 1+
=1.3V 1+
⎛
⎝ ⎜
⎛
⎝ ⎜
R2
R1
R2
R1
+
–
R3
(3.3V ±1.3V)R1
R1
1.3V(R3 + R4)
⎞
⎠ ⎟
HYSTERESIS
= 3.3V
⎞
⎠ ⎟
R3
R1
69453fb