X5323S8IZ-4.5A Intersil, X5323S8IZ-4.5A Datasheet - Page 4

• Manufacturer Part Number: X5323S8IZ-4.5A
• Description: IC CPU SUPERV 32K EE 8-SOIC
• Manufacturer: Intersil
• Type: Simple Reset/Power-On Resetr

Specifications of X5323S8IZ-4.5A

• Number Of Voltages Monitored: 1
• Output: Open Drain or Open Collector
• Reset: Active Low
• Reset Timeout: 100 ms Minimum
• Voltage - Threshold: 4.63V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Descriptions
PIN NUMBER
(SOIC/PDIP)
1
2
5
6
3
4
8
7
PIN NUMBER
3 to 5,10 to 12
TSSOP
14
13
1
2
8
9
6
7
4
PIN NAME
CS/WDI
RESET/
RESET
SCK
V
V
WP
SO
NC
SI
SS
CC
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance
state. Unless a nonvolatile write cycle is underway, the device will be in the stand-by power mode.
CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation
after power-up, a HIGH to LOW transition on CS is required.
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the watchdog timer. The
absence of a HIGH to LOW transition within the watchdog time out period results in
RESET/RESET going active.
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The
falling edge of the serial clock (SCK) clocks the data out.
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this
pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),
addresses and data MSB first.
Serial Clock. The serial clock controls the serial bus timing for data input and output. The rising edge
of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK
changes the data output on the SO pin.
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting
of the watchdog timer control and the memory write protect bits.
Ground
Supply Voltage
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active
whenever V
the minimum V
enabled and CS remains either HIGH or LOW longer than the selectable watchdog time out
period. A falling edge of CS will reset the watchdog timer. RESET/RESET goes active on power-
up at about 1V and remains active for 200ms after the power supply stabilizes.
No internal connections
CC
X5323, X5325
falls below the minimum V
CC
sense level for 200ms. RESET/RESET goes active if the watchdog timer is
PIN FUNCTION
CC
sense level. It will remain active until V
CC
rises above
June 30, 2008
FN8131.2