CAT1021LI-45-G ON Semiconductor, CAT1021LI-45-G Datasheet - Page 10

• Manufacturer Part Number: CAT1021LI-45-G
• Description: IC SUPERVISR CPU 2K EEPROM 8PDIP
• Manufacturer: ON Semiconductor
• Type: Simple Reset/Power-On Resetr

Specifications of CAT1021LI-45-G

• Number Of Voltages Monitored: 1
• Output: Open Drain or Open Collector
• Reset: Active High/Active Low
• Reset Timeout: 130 ms Minimum
• Voltage - Threshold: 4.5V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Monitored Voltage: 3 V, 3.3 V, 5 V
• Undervoltage Threshold: 4.5 V to 4.75 V
• Manual Reset: Resettable
• Watchdog: Watchdog
• Power-up Reset Delay (typ): 200 ms
• Supply Voltage (max): 5 V
• Supply Voltage (min): 2 V
• Supply Current (typ): 3000 uA
• Maximum Power Dissipation: 1000 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CAT1021, CAT1022, CAT1023
ACKNOWLEDGE
After a successful data transfer, each receiving
device is required to generate an acknowledge. The
acknowledging device pulls down the SDA line
during the ninth clock cycle, signaling that it received
the 8 bits of data.
All devices respond with an acknowledge after
receiving a START condition and its slave address.
If the device has been selected along with a write
operation, it responds with an acknowledge after
receiving each 8-bit byte.
When a device begins a READ mode it transmits 8
bits of data, releases the SDA line and monitors the
line for an acknowledge. Once it receives this
acknowledge, the device will continue to transmit
data. If no acknowledge is sent by the Master, the
device terminates data transmission and waits for a
STOP condition.
Figure 5. Start/Stop Timing
Figure 6. Acknowledge Timing
Figure 7: Slave Address Bits
Doc. No. MD-3009 Rev. P
FROM TRANSMITTER
FROM RECEIVER
SDA
SCL
DATA OUTPUT
DATA OUTPUT
SCL FROM
Default Configuration
MASTER
START BIT
START
1
1
0
10
1
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W ¯ ¯ bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
a 8-bit address that is to be written into the address
pointers of the device. After receiving another acknow-
ledge from the Slave, the Master device transmits the
data to be written into the addressed memory location.
The device acknowledges once more and the Master
generates the STOP condition. At this time, the device
begins an internal programming cycle to non-volatile
memory. While the cycle is in progress, the device will
not respond to any request from the Master device.
0
0
8
0
STOP BIT
ACKNOWLEDGE
0
R/W
9
Characteristics subject to change without notice
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