CAT1021LI-45-G ON Semiconductor, CAT1021LI-45-G Datasheet - Page 9

• Manufacturer Part Number: CAT1021LI-45-G
• Description: IC SUPERVISR CPU 2K EEPROM 8PDIP
• Manufacturer: ON Semiconductor
• Type: Simple Reset/Power-On Resetr

Specifications of CAT1021LI-45-G

• Number Of Voltages Monitored: 1
• Output: Open Drain or Open Collector
• Reset: Active High/Active Low
• Reset Timeout: 130 ms Minimum
• Voltage - Threshold: 4.5V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Monitored Voltage: 3 V, 3.3 V, 5 V
• Undervoltage Threshold: 4.5 V to 4.75 V
• Manual Reset: Resettable
• Watchdog: Watchdog
• Power-up Reset Delay (typ): 200 ms
• Supply Voltage (max): 5 V
• Supply Voltage (min): 2 V
• Supply Current (typ): 3000 uA
• Maximum Power Dissipation: 1000 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

EMBEDDED EEPROM OPERATION
The CAT1021/22/23 feature a 2-kbit embedded serial
EEPROM that supports the I
protocol. This Inter-Integrated Circuit Bus protocol
defines any device that sends data to the bus to be a
transmitter and any device receiving data to be a
receiver. The transfer is controlled by the Master
device which generates the serial clock and all
START and STOP conditions for bus access. Both the
Master device and Slave device can operate as either
transmitter or receiver, but the Master device controls
which mode is activated.
I
The features of the I
follows:
(1) Data transfer may be initiated only when the bus
(2) During a data transfer, the data line must remain
START CONDITION
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
Figure 3. Bus Timing
Figure 4. Write Cycle Timing
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
2
C BUS PROTOCOL
is not busy.
stable whenever the clock line is high. Any
changes in the data line while the clock line is
high will be interpreted as a START or STOP
condition.
SCL
SDA
SDA OUT
SDA IN
SCL
2
t SU:STA
C bus protocol are defined as
2
C Bus data transmission
8TH BIT
BYTE n
t F
t HD:STA
t LOW
t AA
ACK
t HD:DAT
t HIGH
t LOW
STOP
CONDITION
9
t DH
SDA when SCL is HIGH. The CAT1021/22/23 monitor
the SDA and SCL lines and will not respond until this
condition is met.
STOP CONDITION
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must
end with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a
START condition. The Master sends the address of
the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are
programmable in metal and the default is 1010.
The last bit of the slave address specifies whether a
Read or Write operation is to be performed. When this
bit is set to 1, a Read operation is selected, and when
set to 0, a Write operation is selected.
After the Master sends a START condition and the
slave address byte, the CAT1021/22/23 monitors the
bus and responds with an acknowledge (on the SDA
line) when its address matches the transmitted slave
address. The CAT1021/22/23 then perform a Read or
Write operation depending on the R/W ¯ ¯ bit.
t SU:DAT
t R
t WR
CAT1021, CAT1022, CAT1023
START
CONDITION
t SU:STO
t BUF
ADDRESS
Doc. No. MD-3009 Rev. P