CAT1640LI-25-G ON Semiconductor, CAT1640LI-25-G Datasheet - Page 8

• Manufacturer Part Number: CAT1640LI-25-G
• Description: IC SUPERVSR CPU 64K EEPROM 8PDIP
• Manufacturer: ON Semiconductor
• Type: Simple Reset/Power-On Resetr

Specifications of CAT1640LI-25-G

• Number Of Voltages Monitored: 1
• Output: Open Drain or Open Collector
• Reset: Active Low
• Reset Timeout: 130 ms Minimum
• Voltage - Threshold: 2.55V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Monitored Voltage: 3 V, 3.3 V, 5 V
• Output Type: Active Low, Open Drain
• Manual Reset: Resettable
• Watchdog: No Watchdog
• Battery Backup Switching: No Backup
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 3 V
• Supply Current (typ): 3000 uA
• Maximum Power Dissipation: 1000 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Undervoltage Threshold: 2.55 V
• Overvoltage Threshold: 2.7 V
• Power-up Reset Delay (typ): 270 ms
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

EMBEDDED EEPROM OPERATION
The CAT1640 and CAT1641 feature a 64kbit
embedded serial EEPROM that supports the I
data transmission protocol. This Inter-Integrated
Circuit Bus protocol defines any device that sends
data to the bus to be a transmitter and any device
receiving data to be a receiver. The transfer is
controlled by the Master device which generates the
serial clock and all START and STOP conditions for
bus access. Both the Master device and Slave device
can operate as either transmitter or receiver, but the
Master device controls which mode is activated.
I
The features of the I
follows:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes in
the data line while the clock line is high will be interpreted
as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
CAT1640, CAT1641
Doc. No. MD-3012, Rev. D
Figure 4. Write Cycle Timing
2
C Bus Protocol
SCL
SDA
2
C bus protocol are defined as
8TH BIT
BYTE n
ACK
2
C Bus
STOP
CONDITION
8
SDA when SCL is HIGH. The CAT1640/41 monitors the
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a START
condition. The Master sends the address of the particular
slave device it is requesting. The four most significant
bits of the 8-bit slave address are programmable in metal
and the default is 1010.
The last bit of the slave address specifies whether a
Read or Write operation is to be performed. When this bit
is set to 1, a Read operation is selected, and when set
to 0, a Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT1640/41 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT1640/41 then performs a Read or Write operation
depending on the R/W bit.
t WR
START
CONDITION
Characteristics subject to change without notice.
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