DS1236S-10N+T&R Maxim Integrated Products, DS1236S-10N+T&R Datasheet - Page 10

• Manufacturer Part Number: DS1236S-10N+T&R
• Description: IC MICROMANAGER 10% 16-SOIC
• Manufacturer: Maxim Integrated Products
• Series: MicroManagerr
• Type: Battery Backup Circuitr

Specifications of DS1236S-10N+T&R

• Number Of Voltages Monitored: 1
• Output: Open Drain, Push-Pull
• Reset: Active High/Active Low
• Reset Timeout: 25 ms Minimum
• Voltage - Threshold: 4.37V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

additional
the supply voltage, as monitored by the IN pin, is above or below a selected operating value. This is
illustrated in Figure 3. As discussed above, the RC pin determines the timing relationships and levels of
several signals. The following section describes the power-up and power-down timing diagrams in more
detail.
TIMING DIAGRAMS
This section provides a description of the timing diagrams shown in Figure 10, Figure 11, Figure 12, and
Figure 13. These diagrams show the relative timing and levels in both the NMOS and the CMOS mode
for power-up and down. Figure 10 illustrates the relationship for power-down in CMOS mode. As V
falls, the IN pin voltage drops below V
failure via an active
V
voltage will follow V
write protect the RAM. When the V
Figure 11 illustrates operation of the power-down sequence in NMOS mode. Once again, as power falls,
an
reaches V
and
loss of battery power.
Figure 12 shows the power-up sequence for the NMOS mode. As V
pins are deactivated. An active reset occurs as well as an
slew rates, reset will be maintained for the standard t
below V
The second
Figure 13 illustrates the power-up timing for CMOS mode. The principal difference is that the DS1236
issues a reset immediately in the NMOS mode. In CMOS mode, a reset is issued when IN rises above
V
WAKE CONTROL/SLEEP CONTROL
The Wake/Sleep Control input (WC/
before entering the Stop mode. This feature allows the DS1236, processor, and static RAM to maintain
nonvolatility in the lowest power mode possible. The processor may invoke the sleep mode in battery
operated applications to conserve battery capacity when an absence of activity is detected. The operation
of this signal is shown in Figure 14. The DS1236 may subsequently be restarted by a high-to-low
transition on the
then be restarted as the watchdog times out and drives RST and
started up by forcing the WC/
sleep mode by the processor and system power is lost, the DS1236 will wake up the next time V
above V
When the sleep mode is invoked during normal power-valid conditions, all operation on the DS1236 is
disabled, thus leaving the
However, a loss of power during a sleep mode will result in an active RST and
grounded (NMOS mode). If the RC pin is tied high, the RST and
CCTP
TP
NMI
. Depending on the processor type, the
PF
, the power monitor trip point. Since the DS1236 is in CMOS mode, no reset is generated. The
will operate in a similar manner to CMOS mode. Notice that the
BAT
TP
is issued. This gives the processor time to save critical data in nonvolatile SRAM. When V
CCTP
, a new
NMI
. These possibilities are illustrated in Figure 15.
NMI
, an active RST and
pulses. In this way, the
PBRST
and RST are provided to illustrate these possibilities.
NMI
NMI
CC
will occur. If the processor does not issue a
input through human interface via a keyboard, touchpad, etc. The processor will
down, but will fall no further than V
, which allows it to enter a sleep mode. As the power falls further, V
NMI
SC
, RST, and
RST
pin high from an external source. Also, if the DS1236 is placed in a
CC
SC
reaches V
are given. The RST voltage will follow V
ST
TP
) allows the processor to disable all comparators on the DS1236
. As a result, the processor is notified of an impending power
NMI
pin can be used to allow the CMOS processor to determine if
RST
may terminate the Stop mode in the processor.
BAT
10 of 19
, a power-fail is issued via the PF and
outputs disabled as well as the
RST
timeout period. At a later time, if the IN pin falls
NMI
BAT
. Although the
. At this time,
RST
RST
ST
CC
, a watchdog reset will also occur.
slews above V
active. The DS1236 can also be
pins will remain inactive during
NMI
NMI
will tri-state to prevent a
RST
CEO
CC
may be short due to
as it falls.
when the RC pin is
BAT
ST
is brought high to
, the PF and
PF
and IN inputs.
pins.
CC
CEO
CC
crosses
DS1236
, PF,
rises
RST
PF
CC
CC