DS1236S-10N+T&R Maxim Integrated Products, DS1236S-10N+T&R Datasheet - Page 6

• Manufacturer Part Number: DS1236S-10N+T&R
• Description: IC MICROMANAGER 10% 16-SOIC
• Manufacturer: Maxim Integrated Products
• Series: MicroManagerr
• Type: Battery Backup Circuitr

Specifications of DS1236S-10N+T&R

• Number Of Voltages Monitored: 1
• Output: Open Drain, Push-Pull
• Reset: Active High/Active Low
• Reset Timeout: 25 ms Minimum
• Voltage - Threshold: 4.37V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

low at the time power-fail detection occurs,
the period t
the corruption of data. If
unconditionally disabled within t
maximum propagation delay of 20 ns. Figure 7 shows a typical nonvolatile SRAM application.
FRESHNESS SEAL
In order to conserve battery capacity during storage and/or shipment of an end system, the DS1236
provides a freshness seal to electrically disconnect the battery. Figure 8 depicts the three pulses below
ground on the IN pin required to invoke the freshness seal. The freshness seal will be disconnected and
normal operation will begin when V
To prevent negative pulses associated with noise from setting the freshness mode in system applications,
a series diode and resistor can be used to shunt noise to ground. During manufacturing, the freshness seal
can still be set by holding TP2 at -3 volts while applying the 0 to –3 volts clock to TP1.
POWER SWITCHING
When larger operating currents are required in a battery backed system, the 5-volt supply and battery
supply switches internal to the DS1236 may not be large enough to support the required load through
V
external power switching devices. As shown in Figure 9, power to the load is switched from V
battery on power-down, and from battery to V
output to switch between V
currently available discrete components. The transition threshold for PF and
battery voltage V
the external switch will be supplied by the battery. Therefore, if a discrete switch is used, this load should
be taken into consideration when sizing the battery.
RESET CONTROL
As mentioned above, the DS1236 supports two modes of operation. The CMOS mode is used when the
system incorporates a CMOS microprocessor which is battery backed. The NMOS mode is used when a
non-battery backed processor is incorporated. The mode is selected by the RC (Reset Control) pin. The
level of this pin distinguishes timing and level control on RST,
processor operation versus nonvolatile battery backup or battery operated processor applications.
ST/INPUT TIMING Figure 2
CCO
with a reasonable voltage drop. For these applications, the PF and
CE
expires. This delay of write protection until the current memory cycle is completed prevents
BAT
, allowing a smooth transition between sources. The load applied to the PF pin from
CEO
BAT
is in an inactive state at the time of V
and V
CF
CC
. During nominal supply conditions
is cycled and reapplied to a level above V
CC
. It provides better leakage and switchover performance than
CEO
CC
6 of 19
is held in its present state until
on power-up. The DS1336 is designed to use the
RST
, and
CC
PF
CEO
fail detection,
outputs are provided to gate
NMI
BAT
PF
will follow
CEI
.
is set to the external
outputs for volatile
is returned high, or
CEO
CEI
will be
DS1236
with a
CC
PF
to