DS1236S-10N+T&R Maxim Integrated Products, DS1236S-10N+T&R Datasheet - Page 9

• Manufacturer Part Number: DS1236S-10N+T&R
• Description: IC MICROMANAGER 10% 16-SOIC
• Manufacturer: Maxim Integrated Products
• Series: MicroManagerr
• Type: Battery Backup Circuitr

Specifications of DS1236S-10N+T&R

• Number Of Voltages Monitored: 1
• Output: Open Drain, Push-Pull
• Reset: Active High/Active Low
• Reset Timeout: 25 ms Minimum
• Voltage - Threshold: 4.37V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

When the RC pin is tied to ground, the DS1236 is designed to interface with NMOS processors which do
not have the microamp currents required during a battery backed mode. Grounding the RC pin does,
however, continue to support nonvolatile backup of system SRAM memory. Nonvolatile systems
incorporating NMOS processors generally require that only the SRAM memory and/or timekeeping
functions be battery backed. When the processor is not battery backed (RC = 0), all signals connected
from the processor to the DS1236 are disconnected from the backup battery supply, or grounded when
system V
giving early warnings with
power-down while isolating the backup battery from the processor during a loss of V
During power-down,
low (NMOS mode), the voltage on
V
voltage below V
V
Removal of an active low level on the
pin is less than V
on the relative voltage relationship between V
ground, the internal timeout will result in a pulse of 200 μs minimum to 500 μs maximum. In contrast, if
the IN pin is tied to V
Connecting the RC pin to a high (V
the system SRAM as well as a low power CMOS processor. When using CMOS microprocessors, it is
possible to place the microprocessor into a very low-power mode termed the “stop” or “halt” mode. In
this state the CMOS processor requires only microamp currents and is fully capable of being battery
backed. This mode generally allows the CMOS microprocessor to maintain the contents of internal RAM
as well as state control of I/O ports during battery backup. The processor can subsequently be restarted by
any of several different signals. To maintain this low-power state, the DS1236 issues no
signals to the processor until it is time to bring the processor back into full operation. To support the low-
power processor battery backed mode (RC = 1), the DS1236 provides a pulsed
failure warning. Waiting to initiate a Stop mode until after the
the processor that no other active
conditions occurs: 1) Voltage on the pin rises above V
below then above V
the processor will be restarted by the reset derived from the watchdog timer as the IN pin rises above V
With the RC pin tied to V
held at a high level via the external battery as V
intended for applications in which the processor is made nonvolatile with an external source, and allows
the processor to power down into a Stop mode as signaled from
output pin will pulse low for t
however,
power-up, RST and
for t
the
NMI
RST
NMI
CC
CC
NMI
RST
up,
rises to V
outputs are driven active and RST will follow V
signal results in an
will enter tri-state (see timing diagram). Also, upon V
. If the IN pin falls below V
RST
output. In addition, as long as the IN pin is less than V
CC
NMI
decays below V
is held low, and both remain active for t
CCTP
will also be held at a high level (V
BAT
TP
. As a result, any potential
), or by the subsequent rise of the IN pin above V
, any detected IN pin levels below V
BAT
RST
CCO
NMI
, which also results in an active RST and
,
NMI
CCO
are held inactive until V
NMI
will pulse low for a minimum of 200 μs, and then return high. If RC is tied
BAT
, RST and
NMI
NMI
pulse of 0 μs minimum to 500 μs maximum during power-up, depending
will not produce a pulse on power-up.
. In the NMOS processor system, the principal emphasis is placed on
, then providing a continuously active RST and RST signal during
following a low voltage detect at the IN pin of V
NMI
TP
NMI
CCO
during an active reset, the reset outputs will be forced inactive by
NMI
) invokes CMOS mode and provides nonvolatile support to both
RST
will follow V
or RST/
pin is controlled by either an internal time-out (when the IN
are not forced active as V
CC
NMI
CC
and the IN pin. As an example, when the IN pin is tied to
9 of 19
falls below battery potential. This mode of operation is
RST
CC
BAT
pulse will not be initiated until V
CC
reaches V
RST
CC
TP
will be issued by the DS1236 until one of two
) by the battery as V
as the supply decays. On power-up, RST follows
, which activates the watchdog, or 2) V
TP
until V
after valid V
are disabled from reaching the
CC
BAT
NMI
TP
NMI
CC
out-of-tolerance at V
, stimulation of the ST pin will result in
RST
, then RST and
supply decays to V
TP
pin has returned high will guarantee
at an earlier voltage level. The
. If V
CC
. The initiation and removal of the
CC
. During a power-up from a V
collapses to V
CC
CC
does not fall below V
decays below V
RST
NMI
CC
TP
.
BAT
CCTP
CC
. Following t
CCTP
NMI
are driven active
for early power
, at which point
reaches V
, the RST and
NMI
. The
and/or reset
CC
pin until
BAT
DS1236
RST
cycles
CCTP
CCTP
NMI
. On
NMI
TP
CC
is
.
.
,
,