CAT1025WI-28-GT3 ON Semiconductor, CAT1025WI-28-GT3 Datasheet - Page 7

• Manufacturer Part Number: CAT1025WI-28-GT3
• Description: IC SUPERVISR CPU 2K EEPROM 8SOIC
• Manufacturer: ON Semiconductor
• Type: Simple Reset/Power-On Resetr

Specifications of CAT1025WI-28-GT3

• Number Of Voltages Monitored: 1
• Output: Open Drain or Open Collector
• Reset: Active High/Active Low
• Reset Timeout: 130 ms Minimum
• Voltage - Threshold: 2.85V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DEVICE OPERATION
Reset Controller Description
The CAT1024/25 precision RESET controllers ensure
correct system operation during brownout and power
up/down conditions. They are configured with open
drain RESET outputs.
During power-up, the RESET outputs remain active
until V
driving the outputs for approximately 200 ms (t
after reaching V
device will cease to drive the reset outputs. At this
point the reset outputs will be pulled up or down by
their respective pull up/down resistors.
During power-down, the RESET outputs will be active
when V
valid so long as V
designed to ignore the fast negative going V
ent pulses (glitches).
Reset output timing is shown in Figure 1.
Manual Reset Operation
The RESET
manual reset input. The input is edge triggered; that
is, the RESET
detecting a high to low transition.
When RESET
200 ms timer will begin to time the reset interval. If
external reset is shorter than 200 ms, Reset outputs
will remain active at least 200 ms.
The CAT1024/25 also have a separate manual reset
input. Driving the MR
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
¯¯¯¯¯¯ pin can operate as reset output and
CC
¯¯¯¯¯¯ I/O is driven to the active state, the
¯¯¯¯¯¯ input will initiate a reset timeout after
CC
reaches the V
falls below V
TH
. After the t
CC
¯¯¯ input low by connecting a
is >1.0 V (V
TH
TH
. The RESET
threshold and will continue
PURST
¯¯¯¯¯¯ output will be
RVALID
timeout interval, the
). The device is
CC
transi-
PURST
)
7
pushbutton (normally open) from MR
generate a reset condition. The input has an internal
pull up resistor.
Reset remains asserted while MR
Reset Timeout period after MR
Glitches shorter than 100 ns on MR
nerate a reset pulse. No external debouncing circuits
are required. Manual reset operation using MR
is shown in Figure 2.
Hardware Data Protection
The CAT1024/25 supervisors have been designed to
solve many of the data corruption issues that have long
been associated with serial EEPROMs. Data corruption
occurs when incorrect data is stored in a memory
location which is assumed to hold correct data.
Whenever the device is in a Reset condition, the
embedded EEPROM is disabled for all operations,
including write operations. If the Reset output(s) are
active, in progress communications to the EEPROM
are aborted and no new communications are allowed.
In this condition an internal write cycle to the memory
can not be started, but an in progress internal non-
volatile memory write cycle can not be aborted. An
internal write cycle initiated before the Reset condition
can be successfully finished if there is enough time
(5 ms) before V
In addition, the CAT1025 includes a Write Protection
Input which when tied to V
operations to the device.
CC
reaches the minimum value of 2 V.
¯¯¯ input has gone high.
CC
CAT1024, CAT1025
¯¯¯ is low and for the
will disable any write
¯¯¯ input will not ge-
¯¯¯ pin to GND will
Doc. No. MD-3008 Rev. R
¯¯¯ input