IC REG LDO ADJ 500MA 8-SOIC

ADP3334ARZ

Manufacturer Part NumberADP3334ARZ
DescriptionIC REG LDO ADJ 500MA 8-SOIC
ManufacturerAnalog Devices Inc
SeriesanyCAP®
ADP3334ARZ datasheet
 


Specifications of ADP3334ARZ

Design ResourcesBroadband Low EVM Direct Conversion Transmitter (CN0134) Broadband Low EVM Direct Conversion Transmitter Using LO Divide-by-2 Modulator (CN0144)Regulator TopologyPositive Adjustable
Voltage - Output1.5 ~ 10 VVoltage - Input2.6 ~ 11 V
Voltage - Dropout (typical)0.2V @ 500mANumber Of Regulators1
Current - Output500mAOperating Temperature-40°C ~ 85°C
Mounting TypeSurface MountPackage / Case8-SOIC (3.9mm Width)
Primary Input Voltage11VOutput Voltage Adjustable Range1.5V To 10V
Dropout Voltage Vdo200mVNo. Of Pins8
Output Current500mAOperating Temperature Range-40°C To +85°C
Lead Free Status / RoHS StatusLead free / RoHS CompliantCurrent - Limit (min)-
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ADP3334
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, device power dissipation should be externally limited
so that junction temperatures will not exceed 150°C.
Calculating Junction Temperature
Device power dissipation is calculated as follows:
(
)
( )
=
-
+
P
V
V
I
V
D
IN
OUT
LOAD
IN
where I
and I
are load current and ground current, V
LOAD
GND
and V
are input and output voltages, respectively.
OUT
Assuming I
= 400 mA, I
= 4 mA, V
LOAD
GND
V
= 2.8 V, device power dissipation is:
OUT
(
)
(
=
-
+
P
5 2 8 400
.
mA
5 0 4
.
mA
D
As an example, the proprietary package used in the ADP3334
has a thermal resistance of 86.6°C/W, significantly lower than
a standard SOIC-8 package. Assuming a 4-layer board, the
junction temperature rise above ambient temperature will be
approximately equal to:
DT = .
¥
=
0 900
W
86 6
.
C W
/
77 9
J
A
To limit the maximum junction temperature to 150°C, maxi-
mum allowable ambient temperature will be:
=
∞ -
=
T
150
C
77 9
.
C / W
72 1
AMAX
The maximum power dissipation versus ambient temperature
for each package is shown in Figure 5.
3.5
48 C/W LFCSP
3.0
2.5
62 C/W LFCSP
2.0
86 C/W SOIC
1.5
122 C/W SOIC
1.0
0.5
158 C/W MSOP
220 C/W MSOP
0
–20
0
20
40
AMBIENT TEMPERATURE – C
Figure 5. Power Derating Curve
Printed Circuit Board Layout Consideration
All surface-mount packages rely on the traces of the PC board
to conduct heat away from the package.
In standard packages, the dominant component of the heat
resistance path is the plastic between the die attach pad and the
individual leads. In typical thermally enhanced packages, one or
more of the leads are fused to the die attach pad, significantly
decreasing this component. To make the improvement mean-
ingful, however, a significant copper area on the PCB must be
attached to these fused pins.
As an example, the patented thermal coastline lead frame design
of the ADP3334 uniformly minimizes the value of the dominant
portion of the thermal resistance. It ensures that heat is con-
ducted away by all pins of the package. This yields a very low
86.6°C/W thermal resistance for the SOIC-8 package, without
any special board layout requirements, relying only on the normal
traces connected to the leads. This yields a 15% improvement in
I
(8)
heat dissipation capability as compared to a standard SOIC-8
GND
package. The thermal resistance can be decreased by an addi-
IN
tional 10% by attaching a few square centimeters of copper area
to the IN or OUT pins of the ADP3334 package.
= 5.0 V and
IN
It is not recommended to use solder mask or silkscreen on the
)
PCB traces adjacent to the ADP3334’s pins since it will increase
=
900
mW
(9)
the junction-to-ambient thermal resistance of the package.
.
C
(10)
.
C
(11)
LFCSP Layout Considerations
The LFCSP package has an exposed die paddle on the bottom,
which efficiently conducts heat to the PCB. In order to achieve
the optimum performance from the LFCSP package, special
consideration must be given to the layout of the PCB. Use the
following layout guidelines for the LFCSP package.
1. The pad pattern is given in Figure 6. The pad dimension
should be followed closely for reliable solder joints while
maintaining reasonable clearances to prevent solder bridging.
2. The thermal pad of the LFCSP package provides a low ther-
60
80
mal impedance path (approximately 20°C/W) to the PCB.
Therefore the PCB must be properly designed to effectively
conduct the heat away from the package. This is achieved by
adding thermal vias to the PCB, which provide a thermal
path to the inner or bottom layers. See Figure 5 for the rec-
ommended via pattern. Note that the via diameter is small to
prevent the solder from flowing through the via and leaving
voids in the thermal pad solder joint.
Note that the thermal pad is attached to the die substrate, so
the thermal planes that the vias attach the package to must
be electrically isolated or connected to V
nect the thermal pad to ground.
–8–
2x VIAS, 0.250
35µm PLATING
0.73
0.30
1.80
0.90
0.50
1.40
1.90
3.36
Figure 6. 3 mm x 3 mm LFCSP Pad Pattern
(Dimensions shown in millimeters)
. Do NOT con-
IN
2.36
REV. B