AT91SAM7S64C-AU Atmel, AT91SAM7S64C-AU Datasheet - Page 105

• Manufacturer Part Number: AT91SAM7S64C-AU
• Description: IC ARM7 MCU 32BIT 64K 64LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S64C-AU

• Package / Case: 64-LQFP
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 55MHz
• Number Of I /o: 32
• Core Processor: ARM7
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, SPI, SSC, UART/USART, USB
• Core Size: 16/32-Bit
• Core: ARM7TDMI
• Package: 64LQFP
• Device Core: ARM7TDMI
• Family Name: AT91
• Maximum Speed: 55 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 32
• Interface Type: SPI/TWI/USART/USB
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT91SAM7S64B-AU::AT91SAM7S64B-AU

19. Embedded Flash Controller (EFC)
19.1
19.2
19.2.1
Table 19-1.
6175K–ATARM–30-Aug-10
AT91SAM7S
512
32
2
Overview
Functional Description
Embedded Flash Organization
AT91SAM7S
Product Specific Lock and General-purpose NVM Bits
256
16
2
AT91SAM7S
The Embedded Flash Controller (EFC ) is a part of the Memory Controller and ensures the inter-
face of the Flash block with the 32-bit internal bus. It increases performance in Thumb Mode for
Code Fetch with its system of 32-bit buffers. It also manages the programming, erasing, locking
and unlocking sequences using a full set of commands.
The AT91SAM7S512 is equipped with two EFCs, EFC0 and EFC1. EFC1 does not feature the
Security bit and GPNVM bit. The Security and GPNVM bits embedded only on EFC0 apply to
the two blocks in the AT91SAM7S512.
The Embedded Flash interfaces directly to the 32-bit internal bus. It is composed of several
interfaces:
The Embedded Flash size, the page size and the lock region organization are described in the
product definition section.
• One memory plane organized in several pages of the same size
• Two 32-bit read buffers used for code read optimization (see
• One write buffer that manages page programming. The write buffer size is equal to the page
• Several lock bits used to protect write and erase operations on lock regions. A lock region is
• Several general-purpose NVM bits. Each bit controls a specific feature in the device. Refer to
107).
size. This buffer is write-only and accessible all along the 1 MByte address space, so that
each word can be written to its final address (see
composed of several consecutive pages, and each lock region has its associated lock bit.
the product definition section to get the GPNVM assignment.
128
2
8
AT91SAM7S
64
16
2
AT91SAM7S
321
2
8
AT91SAM7S Series Preliminary
AT91SAM7S
32
2
8
AT91SAM7S
“Write Operations” on page
161
2
8
AT91SAM7S
“Read Operations” on page
16
2
8
Number of GPNVM bits
Number of Lock Bits
Denomination
109).
105