AT91SAM7S64C-AU Atmel, AT91SAM7S64C-AU Datasheet - Page 615

• Manufacturer Part Number: AT91SAM7S64C-AU
• Description: IC ARM7 MCU 32BIT 64K 64LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S64C-AU

• Package / Case: 64-LQFP
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 55MHz
• Number Of I /o: 32
• Core Processor: ARM7
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, SPI, SSC, UART/USART, USB
• Core Size: 16/32-Bit
• Core: ARM7TDMI
• Package: 64LQFP
• Device Core: ARM7TDMI
• Family Name: AT91
• Maximum Speed: 55 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 32
• Interface Type: SPI/TWI/USART/USB
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT91SAM7S64B-AU::AT91SAM7S64B-AU

40.6.2.11
40.6.3
40.6.3.1
40.6.4
40.6.4.1
6175K–ATARM–30-Aug-10
Master Clock (MCK)
Non Volatile Memory Bits (NVM Bits)
ADC: Sleep Mode
MCK: Limited Master Clock Frequency Ranges
NVM Bits: Write/Erase Cycles Number
None.
If Sleep mode is activated while there is no activity (no conversion is being performed), it will
take effect only after a conversion occurs.
To activate sleep mode as soon as possible, it is recommended to write successively, ADC
Mode Register (SLEEP) then ADC Control Register (START bit field); to start an analog-to-digi-
tal conversion, in order put ADC into sleep mode at the end of this conversion.
If the Flash is operating without wait states, the frequency of the Master Clock MCK must be
lower than 3 MHz or higher than 19 MHz.
If the Flash is operating with one wait state, the frequency of the Master Clock MCK must be
lower than 3 MHz or higher than 19 MHz.
If the Flash is operating with two wait states, the frequency of the Master Clock MCK must be
lower than 3 MHz or higher than 25 MHz.
If the Flash is operating with three wait states, the frequency of the Master Clock MCK must be
lower than 3 MHz or higher than 38 MHz.
If these constraints are not respected, the correct operation of the system cannot be guaranteed
and either data or prefetch abort might occur.
The maximum operating frequencies (at 30 MHz @ 0 Wait States and 55 MHz @ 1 Wait State)
as stated in
Note:
The user must ensure that the device is running at the authorized frequency by programming the
PLL properly to not run within the forbidden frequency range.
The maximum number of write/erase cycles for Non Volatile Memory bits is 100. This includes
Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit.
This maximum number of write/erase cycles is not applicable to 256 KB Flash memory, it
remains at 10K for the Flash memory.
None.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
It is not necessary to use 2 o 3 wait states because the Flash can operate at maximum frequency
with only 1 wait state.
Table 37-24, “Embedded Flash Wait States,” on page
AT91SAM7S Series Preliminary
578, are still applicable.
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